mirror of
https://github.com/coolsnowwolf/lede.git
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63 lines
2.3 KiB
Diff
63 lines
2.3 KiB
Diff
From ce9e56a436e486690097cfbdda2d0c11b60db4c2 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:12 +0800
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Subject: [PATCH] clk: gcc-ipq5018: refer to GE PHY rx and tx clk providers by name
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QCA-SSDK does not register the output clocks of the onboard GE Phy and
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uniphy so the GCC and DTS can't reference them by their index.
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The SSDK references them by name, so let's change the GCC driver
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accordingly.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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drivers/clk/qcom/gcc-ipq5018.c | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq5018.c
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+++ b/drivers/clk/qcom/gcc-ipq5018.c
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@@ -335,8 +335,8 @@ static const struct parent_map gcc_xo_gp
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static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_GEPHY_RX_CLK },
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- { .index = DT_GEPHY_TX_CLK },
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+ { .name = "gephy_gcc_rx", .index = -1 },
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+ { .name = "gephy_gcc_tx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -351,8 +351,8 @@ static const struct parent_map gcc_xo_ge
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static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_GEPHY_TX_CLK },
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- { .index = DT_GEPHY_RX_CLK },
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+ { .name = "gephy_gcc_tx", .index = -1 },
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+ { .name = "gephy_gcc_rx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -367,8 +367,8 @@ static const struct parent_map gcc_xo_ge
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static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_UNIPHY_RX_CLK },
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- { .index = DT_UNIPHY_TX_CLK },
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+ { .name = "uniphy_gcc_rx", .index = -1 },
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+ { .name = "uniphy_gcc_tx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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@@ -383,8 +383,8 @@ static const struct parent_map gcc_xo_un
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static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {
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{ .index = DT_XO },
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- { .index = DT_UNIPHY_TX_CLK },
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- { .index = DT_UNIPHY_RX_CLK },
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+ { .name = "uniphy_gcc_tx", .index = -1 },
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+ { .name = "uniphy_gcc_rx", .index = -1 },
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{ .hw = &ubi32_pll.clkr.hw },
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{ .hw = &gpll0.clkr.hw },
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};
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