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86 lines
2.0 KiB
Diff
86 lines
2.0 KiB
Diff
From: Varadarajan Narayanan <quic_varada@quicinc.com>
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Date: Thu, 2 Jan 2025 17:00:15 +0530
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Subject: [PATCH] dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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---
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
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@@ -0,0 +1,71 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm UNIPHY PCIe 28LP PHY
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+
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+maintainers:
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+ - Nitheesh Sekar <quic_nsekar@quicinc.com>
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+ - Varadarajan Narayanan <quic_varada@quicinc.com>
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+
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+description:
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+ PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq5332-uniphy-pcie-phy
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: pcie pipe clock
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+ - description: pcie ahb clock
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+
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+ resets:
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+ items:
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+ - description: phy reset
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+ - description: ahb reset
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+ - description: cfg reset
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+
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+ "#phy-cells":
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+ const: 0
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+
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+ "#clock-cells":
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+ const: 0
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+
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+ num-lanes: true
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - resets
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+ - "#phy-cells"
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+ - "#clock-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
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+
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+ pcie0_phy: phy@4b0000 {
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+ compatible = "qcom,ipq5332-uniphy-pcie-phy";
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+ reg = <0x004b0000 0x800>;
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+
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+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
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+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
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+
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+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
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+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>,
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+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>;
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+
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+ #clock-cells = <0>;
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+
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+ #phy-cells = <0>;
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+ };
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