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87 lines
2.3 KiB
Diff
87 lines
2.3 KiB
Diff
From e7166f2774aafefd29ff26ffbbb7f6d40ac8ea1c Mon Sep 17 00:00:00 2001
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From: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Date: Mon, 4 Sep 2023 12:06:34 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add USB related nodes
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Add USB phy and controller nodes.
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Co-developed-by: Amandeep Singh <quic_amansing@quicinc.com>
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Signed-off-by: Amandeep Singh <quic_amansing@quicinc.com>
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Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
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Link: https://lore.kernel.org/r/20230904063635.24975-4-quic_nsekar@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -94,6 +94,19 @@
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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+ usbphy0: phy@5b000 {
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+ compatible = "qcom,ipq5018-usb-hsphy";
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+ reg = <0x0005b000 0x120>;
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+
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+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
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+
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+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
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+
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+ #phy-cells = <0>;
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+
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+ status = "disabled";
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+ };
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+
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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@@ -156,6 +169,47 @@
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status = "disabled";
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};
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+ usb: usb@8af8800 {
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+ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
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+ reg = <0x08af8800 0x400>;
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+
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+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hs_phy_irq";
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+
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+ clocks = <&gcc GCC_USB0_MASTER_CLK>,
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+ <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
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+ <&gcc GCC_USB0_SLEEP_CLK>,
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+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
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+ clock-names = "core",
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+ "iface",
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+ "sleep",
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+ "mock_utmi";
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+
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+ resets = <&gcc GCC_USB0_BCR>;
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+
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+ qcom,select-utmi-as-pipe-clk;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ status = "disabled";
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+
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+ usb_dwc: usb@8a00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x08a00000 0xe000>;
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+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
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+ clock-names = "ref";
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+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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+ phy-names = "usb2-phy";
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+ phys = <&usbphy0>;
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+ tx-fifo-resize;
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+ snps,is-utmi-l1-suspend;
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+ snps,hird-threshold = /bits/ 8 <0x0>;
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+ snps,dis_u2_susphy_quirk;
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+ snps,dis_u3_susphy_quirk;
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+ };
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+ };
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+
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x0b000000 0x1000>, /* GICD */
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