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8cb632045f
Due to the missing ATF for normally boot, there are still a lot of bugs on this platform. At the same time, the GMAC driver also lacks a part.
80 lines
2.8 KiB
Diff
80 lines
2.8 KiB
Diff
From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sat, 5 Mar 2022 16:58:35 -0500
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Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
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The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
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hardware supports. This leads to a situation during card initialization
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where the clock is set lower than the clock driver can support. The
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dw-mmc-rockchip driver spews errors when this happens.
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For normal operation this only happens a few times during boot, but when
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cd-broken is enabled (in cases such as the SoQuartz module) this fires
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multiple times each poll cycle.
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Fix this by testing the lowest possible frequency that the clock driver
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can support which is within the mmc specification. Divide that rate by
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the internal divider and set f_min to this.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
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1 file changed, 23 insertions(+), 4 deletions(-)
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -15,7 +15,9 @@
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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-#define RK3288_CLKGEN_DIV 2
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+#define RK3288_CLKGEN_DIV 2
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+
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+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
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struct dw_mci_rockchip_priv_data {
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struct clk *drv_clk;
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@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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ret = clk_set_rate(host->ciu_clk, cclkin);
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if (ret)
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- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
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+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
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bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
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if (bus_hz != host->bus_hz) {
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@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
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static int dw_mci_rockchip_init(struct dw_mci *host)
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{
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+ int ret, i;
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+
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/* It is slot 8 on Rockchip SoCs */
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host->sdio_id0 = 8;
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- if (of_device_is_compatible(host->dev->of_node,
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- "rockchip,rk3288-dw-mshc"))
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+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
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host->bus_hz /= RK3288_CLKGEN_DIV;
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+ /* clock driver will fail if the clock is less than the lowest source clock
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+ * divided by the internal clock divider. Test for the lowest available
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+ * clock and set the minimum freq to clock / clock divider.
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+ */
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+
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+ for (i = 0; i < ARRAY_SIZE(freqs); i++) {
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+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
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+ if (ret > 0) {
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+ host->minimum_speed = ret / RK3288_CLKGEN_DIV;
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+ break;
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+ }
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+ }
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+ if (ret < 0)
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+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
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+ }
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+
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return 0;
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}
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