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8b14c27843
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
113 lines
4.5 KiB
Diff
113 lines
4.5 KiB
Diff
From 2a011c3c12e8de461fb1fdce85fa38d308c4eb8b Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Sat, 29 Jun 2024 19:51:49 +0200
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Subject: [PATCH] phy: airoha: Add dtime and Rx AEQ IO registers
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Introduce Tx-Rx detection Time and Rx AEQ training mappings to
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phy-airoha-pcie driver. This is a preliminary patch to introduce PCIe
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support to En7581 SoC through the mediatek-gen3 PCIe driver.
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This change is not introducing any backward compatibility issue since
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the EN7581 dts is not upstream yet.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Link: https://lore.kernel.org/r/edf3b28926177166c65256604d69f2f576cb6fb3.1719682943.git.lorenzo@kernel.org
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/phy-airoha-pcie-regs.h | 17 +++++++++++++
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drivers/phy/phy-airoha-pcie.c | 38 ++++++++++++++++++++++++++++++
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2 files changed, 55 insertions(+)
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--- a/drivers/phy/phy-airoha-pcie-regs.h
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+++ b/drivers/phy/phy-airoha-pcie-regs.h
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@@ -474,4 +474,21 @@
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#define REG_PCIE_PMA_DIG_RESERVE_27 0x0908
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#define REG_PCIE_PMA_DIG_RESERVE_30 0x0914
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+/* DTIME */
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+#define REG_PCIE_PEXTP_DIG_GLB44 0x00
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+#define PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL GENMASK(7, 0)
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+#define PCIE_XTP_RXDET_EN_STB_T_SEL GENMASK(15, 8)
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+#define PCIE_XTP_RXDET_FINISH_STB_T_SEL GENMASK(23, 16)
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+#define PCIE_XTP_TXPD_TX_DATA_EN_DLY GENMASK(27, 24)
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+#define PCIE_XTP_TXPD_RXDET_DONE_CDT BIT(28)
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+#define PCIE_XTP_RXDET_LATCH_STB_T_SEL GENMASK(31, 29)
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+
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+/* RX AEQ */
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+#define REG_PCIE_PEXTP_DIG_LN_RX30_P0 0x0000
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+#define PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT GENMASK(7, 0)
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+#define PCIE_XTP_LN_RX_PDOWN_T2RLB_DIG_EN BIT(8)
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+#define PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT GENMASK(31, 16)
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+
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+#define REG_PCIE_PEXTP_DIG_LN_RX30_P1 0x0100
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+
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#endif /* _PHY_AIROHA_PCIE_H */
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--- a/drivers/phy/phy-airoha-pcie.c
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+++ b/drivers/phy/phy-airoha-pcie.c
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@@ -31,6 +31,9 @@ enum airoha_pcie_port_gen {
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* @csr_2l: Analogic lane IO mapped register base address
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* @pma0: IO mapped register base address of PMA0-PCIe
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* @pma1: IO mapped register base address of PMA1-PCIe
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+ * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time
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+ * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time
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+ * @rx_aeq: IO mapped register base address of Rx AEQ training
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*/
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struct airoha_pcie_phy {
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struct device *dev;
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@@ -38,6 +41,9 @@ struct airoha_pcie_phy {
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void __iomem *csr_2l;
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void __iomem *pma0;
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void __iomem *pma1;
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+ void __iomem *p0_xr_dtime;
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+ void __iomem *p1_xr_dtime;
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+ void __iomem *rx_aeq;
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};
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static void airoha_phy_clear_bits(void __iomem *reg, u32 mask)
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@@ -1101,6 +1107,21 @@ static void airoha_pcie_phy_load_kflow(s
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static int airoha_pcie_phy_init(struct phy *phy)
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{
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struct airoha_pcie_phy *pcie_phy = phy_get_drvdata(phy);
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+ u32 val;
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+
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+ /* Setup Tx-Rx detection time */
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+ val = FIELD_PREP(PCIE_XTP_RXDET_VCM_OFF_STB_T_SEL, 0x33) |
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+ FIELD_PREP(PCIE_XTP_RXDET_EN_STB_T_SEL, 0x1) |
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+ FIELD_PREP(PCIE_XTP_RXDET_FINISH_STB_T_SEL, 0x2) |
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+ FIELD_PREP(PCIE_XTP_TXPD_TX_DATA_EN_DLY, 0x3) |
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+ FIELD_PREP(PCIE_XTP_RXDET_LATCH_STB_T_SEL, 0x1);
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+ writel(val, pcie_phy->p0_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
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+ writel(val, pcie_phy->p1_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44);
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+ /* Setup Rx AEQ training time */
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+ val = FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_L1P2_EXIT_WAIT, 0x32) |
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+ FIELD_PREP(PCIE_XTP_LN_RX_PDOWN_E0_AEQEN_WAIT, 0x5050);
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+ writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P0);
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+ writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P1);
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/* enable load FLL-K flow */
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airoha_phy_pma0_set_bits(pcie_phy, REG_PCIE_PMA_DIG_RESERVE_14,
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@@ -1217,6 +1238,23 @@ static int airoha_pcie_phy_probe(struct
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return dev_err_probe(dev, PTR_ERR(pcie_phy->phy),
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"Failed to create PCIe phy\n");
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+ pcie_phy->p0_xr_dtime =
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+ devm_platform_ioremap_resource_byname(pdev, "p0-xr-dtime");
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+ if (IS_ERR(pcie_phy->p0_xr_dtime))
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+ return dev_err_probe(dev, PTR_ERR(pcie_phy->p0_xr_dtime),
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+ "Failed to map P0 Tx-Rx dtime base\n");
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+
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+ pcie_phy->p1_xr_dtime =
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+ devm_platform_ioremap_resource_byname(pdev, "p1-xr-dtime");
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+ if (IS_ERR(pcie_phy->p1_xr_dtime))
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+ return dev_err_probe(dev, PTR_ERR(pcie_phy->p1_xr_dtime),
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+ "Failed to map P1 Tx-Rx dtime base\n");
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+
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+ pcie_phy->rx_aeq = devm_platform_ioremap_resource_byname(pdev, "rx-aeq");
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+ if (IS_ERR(pcie_phy->rx_aeq))
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+ return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq),
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+ "Failed to map Rx AEQ base\n");
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+
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pcie_phy->dev = dev;
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phy_set_drvdata(pcie_phy->phy, pcie_phy);
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