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dbf85c4248
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.12, as well as a couple boards equipped with these. Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
From 907f68f5000522e3c78e9a5dca194f52f2ac54d3 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sun, 31 Oct 2021 17:15:58 +0100
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Subject: [PATCH 1000/1021] riscv: dts: starfive: Add JH7100 high speed UARTs
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Add missing device tree nodes for UART0 and UART1 on the StarFive JH7100
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SoC. UART0 is used for Bluetooth on the BeagleV Starlight and StarFive
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VisionFive V1 boards.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 ++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -258,6 +258,32 @@
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reg = <0x0 0x11850000 0x0 0x10000>;
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};
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+ uart0: serial@11870000 {
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+ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
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+ reg = <0x0 0x11870000 0x0 0x10000>;
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+ clocks = <&clkgen JH7100_CLK_UART0_CORE>,
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+ <&clkgen JH7100_CLK_UART0_APB>;
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+ clock-names = "baudclk", "apb_pclk";
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+ resets = <&rstgen JH7100_RSTN_UART0_APB>;
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+ interrupts = <92>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@11880000 {
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+ compatible = "starfive,jh7100-hsuart", "snps,dw-apb-uart";
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+ reg = <0x0 0x11880000 0x0 0x10000>;
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+ clocks = <&clkgen JH7100_CLK_UART1_CORE>,
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+ <&clkgen JH7100_CLK_UART1_APB>;
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+ clock-names = "baudclk", "apb_pclk";
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+ resets = <&rstgen JH7100_RSTN_UART1_APB>;
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+ interrupts = <93>;
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+ reg-io-width = <4>;
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+ reg-shift = <2>;
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+ status = "disabled";
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+ };
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+
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i2c0: i2c@118b0000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x118b0000 0x0 0x10000>;
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