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https://github.com/coolsnowwolf/lede.git
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dbf85c4248
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.12, as well as a couple boards equipped with these. Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
177 lines
4.1 KiB
Diff
177 lines
4.1 KiB
Diff
From 5605ebdd7f7033da8f1bcb77cb180ef16235d5c8 Mon Sep 17 00:00:00 2001
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From: Hal Feng <hal.feng@starfivetech.com>
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Date: Tue, 11 Apr 2023 16:31:15 +0800
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Subject: [PATCH 01/55] riscv: dts: starfive: Add full support (except VIN and
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VOUT) for JH7110 and VisionFive 2 board
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Merge all StarFive dts patches together except VIN and VOUT.
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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---
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.../boot/dts/starfive/jh7110-common.dtsi | 2 +
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.../jh7110-starfive-visionfive-2.dtsi | 100 ++++++++++++++++++
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arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++
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3 files changed, 123 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
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@@ -18,6 +18,8 @@
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i2c6 = &i2c6;
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mmc0 = &mmc0;
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mmc1 = &mmc1;
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+ pcie0 = &pcie0;
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+ pcie1 = &pcie1;
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serial0 = &uart0;
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};
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--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -29,6 +29,24 @@
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};
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};
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+&i2srx {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2srx_pins>;
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+ status = "okay";
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+};
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+
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+&i2stx0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mclk_ext_pins>;
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+ status = "okay";
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+};
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+
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+&i2stx1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&i2stx1_pins>;
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+ status = "okay";
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+};
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+
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&mmc0 {
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non-removable;
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};
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@@ -40,3 +58,85 @@
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&pcie1 {
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status = "okay";
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};
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+
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+&sysgpio {
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+ i2srx_pins: i2srx-0 {
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+ clk-sd-pins {
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+ pinmux = <GPIOMUX(38, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_I2SRX_BCLK)>,
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+ <GPIOMUX(63, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_I2SRX_LRCK)>,
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+ <GPIOMUX(38, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_I2STX1_BCLK)>,
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+ <GPIOMUX(63, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_I2STX1_LRCK)>,
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+ <GPIOMUX(61, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_I2SRX_SDIN0)>;
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+ input-enable;
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+ };
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+ };
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+
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+ i2stx1_pins: i2stx1-0 {
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+ sd-pins {
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+ pinmux = <GPIOMUX(44, GPOUT_SYS_I2STX1_SDO0,
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+ GPOEN_ENABLE,
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+ GPI_NONE)>;
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+ bias-disable;
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+ input-disable;
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+ };
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+ };
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+
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+ mclk_ext_pins: mclk-ext-0 {
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+ mclk-ext-pins {
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+ pinmux = <GPIOMUX(4, GPOUT_LOW,
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+ GPOEN_DISABLE,
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+ GPI_SYS_MCLK_EXT)>;
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+ input-enable;
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+ };
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+ };
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+
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+ tdm_pins: tdm-0 {
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+ tx-pins {
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+ pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD,
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+ GPOEN_ENABLE,
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+ GPI_NONE)>;
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+ bias-pull-up;
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+ drive-strength = <2>;
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+ input-disable;
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+ input-schmitt-disable;
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+ slew-rate = <0>;
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+ };
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+
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+ rx-pins {
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+ pinmux = <GPIOMUX(61, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_RXD)>;
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+ input-enable;
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+ };
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+
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+ sync-pins {
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+ pinmux = <GPIOMUX(63, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_SYNC)>;
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+ input-enable;
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+ };
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+
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+ pcmclk-pins {
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+ pinmux = <GPIOMUX(38, GPOUT_HIGH,
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+ GPOEN_DISABLE,
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+ GPI_SYS_TDM_CLK)>;
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+ input-enable;
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+ };
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+ };
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+};
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+
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+&tdm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&tdm_pins>;
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+ status = "okay";
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+};
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--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -259,6 +259,7 @@
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clock-output-names = "dvp_clk";
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#clock-cells = <0>;
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};
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+
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gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
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compatible = "fixed-clock";
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clock-output-names = "gmac0_rgmii_rxin";
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@@ -919,6 +920,26 @@
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#gpio-cells = <2>;
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};
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+ timer@13050000 {
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+ compatible = "starfive,jh7110-timer";
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+ reg = <0x0 0x13050000 0x0 0x10000>;
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+ interrupts = <69>, <70>, <71>, <72>;
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+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
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+ <&syscrg JH7110_SYSCLK_TIMER0>,
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+ <&syscrg JH7110_SYSCLK_TIMER1>,
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+ <&syscrg JH7110_SYSCLK_TIMER2>,
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+ <&syscrg JH7110_SYSCLK_TIMER3>;
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+ clock-names = "apb", "ch0", "ch1",
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+ "ch2", "ch3";
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+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
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+ <&syscrg JH7110_SYSRST_TIMER0>,
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+ <&syscrg JH7110_SYSRST_TIMER1>,
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+ <&syscrg JH7110_SYSRST_TIMER2>,
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+ <&syscrg JH7110_SYSRST_TIMER3>;
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+ reset-names = "apb", "ch0", "ch1",
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+ "ch2", "ch3";
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+ };
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+
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watchdog@13070000 {
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compatible = "starfive,jh7110-wdt";
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reg = <0x0 0x13070000 0x0 0x10000>;
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