mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
212 lines
6.2 KiB
Diff
212 lines
6.2 KiB
Diff
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
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+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
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@@ -55,6 +55,7 @@
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writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
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writel(0x10001, 0x030017ac);
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+ writel(0x80004, 0x0300a104);
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writel(0x50, 0x0300a028);
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writel(0x20, 0x0300a040);
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}
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--- a/board/sunxi/board.c
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+++ b/board/sunxi/board.c
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@@ -574,10 +574,13 @@
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spl->dram_size = dram_size >> 20;
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}
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+#define sunxi_ac300_key (1<<8)
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+
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void sunxi_board_init(void)
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{
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int power_failed = 0;
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u8 data[2];
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+ int val;
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#ifdef CONFIG_LED_STATUS
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if (IS_ENABLED(CONFIG_SPL_DRIVERS_MISC))
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@@ -667,25 +670,33 @@
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*/
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if (!power_failed)
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clock_set_pll1(get_board_sys_clk());
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- else
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- printf("Failed to set core voltage! Can't set CPU frequency\n");
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+ else {
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+ clock_set_pll1(792000000);
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+ printf("Failed to set core voltage! set CPU 792000000hz frequency\n");
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+ }
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- i2c_set_bus_num(1);
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- data[0] = 0;
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- data[1] = 0;
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- i2c_write(0x10, 0xfe, 1, data, 2);
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- i2c_write(0x10, 2, 1, data, 2);
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- data[1] = 1;
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- i2c_write(0x10, 2, 1, data, 2);
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- data[1] = 0xf;
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- i2c_write(0x10, 0x16, 1, data, 2);
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- data[1] = 3;
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- i2c_write(0x10, 0x14, 1, data, 2);
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- data[1] = 0x60;
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- i2c_write(0x10, 0xfe, 1, data, 2);
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- data[0] = 0x08;
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- data[1] = 0x14;
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- i2c_write(0x10, 0, 1, data, 2);
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+#if CONFIG_IS_ENABLED(SPL_I2C) && CONFIG_IS_ENABLED(SPL_SYS_I2C_LEGACY)
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+ val=readl(0x300622c);
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+ if((val&sunxi_ac300_key)==0)
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+ {
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+ i2c_set_bus_num(1);
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+ data[0] = 0;
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+ data[1] = 0;
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+ i2c_write(0x10, 0xfe, 1, data, 2);
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+ i2c_write(0x10, 2, 1, data, 2);
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+ data[1] = 1;
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+ i2c_write(0x10, 2, 1, data, 2);
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+ data[1] = 0xf;
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+ i2c_write(0x10, 0x16, 1, data, 2);
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+ data[1] = 3;
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+ i2c_write(0x10, 0x14, 1, data, 2);
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+ data[1] = 0x60;
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+ i2c_write(0x10, 0xfe, 1, data, 2);
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+ data[0] = 0x08;
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+ data[1] = 0x14;
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+ i2c_write(0x10, 0, 1, data, 2);
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+ }
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+#endif
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}
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#endif /* CONFIG_SPL_BUILD */
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--- a/drivers/net/phy/phy.c
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+++ b/drivers/net/phy/phy.c
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@@ -16,6 +16,7 @@
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#include <command.h>
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#include <miiphy.h>
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#include <phy.h>
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+#include <asm/io.h>
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#include <errno.h>
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#include <asm/global_data.h>
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#include <dm/of_extra.h>
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@@ -384,10 +385,79 @@
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return 0;
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}
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+static void disable_intelligent_ieee(struct phy_device *phydev)
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+{
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+ unsigned int value;
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0100); /* switch to page 1 */
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+ value = phy_read(phydev, MDIO_DEVAD_NONE, 0x17); /* read address 0 0x17 register */
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+ value &= ~(1 << 3); /* reg 0x17 bit 3, set 0 to disable IEEE */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, value);
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+ phy_write(phydev, MDIO_DEVAD_NONE,0x1f, 0x0000); /* switch to page 0 */
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+}
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+
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+static void disable_802_3az_ieee(struct phy_device *phydev)
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+{
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+ unsigned int value;
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x3c);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x1 << 14 | 0x7);
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+ value = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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+ value &= ~(0x1 << 1);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x3c);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x1 << 14 | 0x7);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, value);
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0200); /* switch to page 2 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0x0000);
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+}
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+
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+static void ephy_config_default(struct phy_device *phydev)
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+{
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0100); /* Switch to Page 1 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x12, 0x4824); /* Disable APS */
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0200); /* Switch to Page 2 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0x0000); /* PHYAFE TRX optimization */
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0600); /* Switch to Page 6 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x708b); /* PHYAFE TX optimization */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x13, 0xF000); /* PHYAFE RX optimization */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1530);
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0800); /* Switch to Page 6 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0x00bc); /* PHYAFE TRX optimization */
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+}
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+
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+static void __maybe_unused ephy_config_fixed(struct phy_device *phydev)
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+{
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0100); /*switch to Page 1 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x12, 0x4824); /*Disable APS */
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0200); /*switch to Page 2 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0x0000); /*PHYAFE TRX optimization */
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0600); /*switch to Page 6 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x7809); /*PHYAFE TX optimization */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x13, 0xf000); /*PHYAFE RX optimization */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x5523);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x3533);
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+
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0800); /*switch to Page 8 */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x0844); /*disable auto offset */
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0x00bc); /*PHYAFE TRX optimization */
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+
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+}
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+
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+#define sunxi_ac300_key (1<<8)
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+
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int genphy_config(struct phy_device *phydev)
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{
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int val;
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u32 features;
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+ u16 sid_value;
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features = (SUPPORTED_TP | SUPPORTED_MII
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| SUPPORTED_AUI | SUPPORTED_FIBRE |
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@@ -432,6 +502,42 @@
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genphy_config_aneg(phydev);
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+ val=readl(0x300622c);
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+ sid_value=0xffff&val;
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+ if(val&sunxi_ac300_key)
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+ {
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+ /*add quirk for h313/H616 emac1 ephy bb version bug*/
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+ /*printf("apply fix for AC300 ephy bb version bug ...\n");*/
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1f83);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1fb7);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 5, 0xa81f);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 6, 0);
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+ udelay(500000);
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+
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+ val=phy_read(phydev, MDIO_DEVAD_NONE, 6);
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+ val&=~(0x0f<<12);
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+ val|=(0x0f&(0x03+sid_value))<<12;
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+ phy_write(phydev,MDIO_DEVAD_NONE, 6,val);
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+
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+ if(sid_value&0x200) {
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+ /*printf("using AC300 emac1 ephy fixed config ...\n");*/
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+ ephy_config_fixed(phydev);
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+ }
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+ else {
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+ /*printf("using AC300 emac1 ephy default config ...\n");*/
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+ ephy_config_default(phydev);
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+ }
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+
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+ disable_intelligent_ieee(phydev);
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+
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+ disable_802_3az_ieee(phydev);
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+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0000);
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+
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+ val=phy_read(phydev, MDIO_DEVAD_NONE, 6);
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+ val|=(0x1<<11);
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+ phy_write(phydev,MDIO_DEVAD_NONE, 6,val);
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+ /*add end*/
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+ }
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return 0;
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}
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