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261 lines
8.3 KiB
Diff
261 lines
8.3 KiB
Diff
From 59903441f5e49d46478fefcccec41e2ba896b740 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Wed, 28 Aug 2024 15:24:55 +0000
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Subject: [PATCH] mmc: dw_mmc-rockchip: Add internal phase support
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Some Rockchip devices put the phase settings into the dw_mmc controller.
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When the feature is present, the ciu-drive and ciu-sample clocks are
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not used and the phase configuration is done directly through the mmc
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controller.
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/010201919996fdae-8a9f843e-00a8-4131-98bf-a9da4ed04bfd-000000@eu-west-1.amazonses.com
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++--
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1 file changed, 160 insertions(+), 11 deletions(-)
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--- a/drivers/mmc/host/dw_mmc-rockchip.c
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+++ b/drivers/mmc/host/dw_mmc-rockchip.c
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@@ -15,7 +15,17 @@
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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-#define RK3288_CLKGEN_DIV 2
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+#define RK3288_CLKGEN_DIV 2
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+#define SDMMC_TIMING_CON0 0x130
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+#define SDMMC_TIMING_CON1 0x134
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+#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
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+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
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+#define ROCKCHIP_MMC_DEGREE_OFFSET 1
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+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
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+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
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+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
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+#define HIWORD_UPDATE(val, mask, shift) \
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+ ((val) << (shift) | (mask) << ((shift) + 16))
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static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
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@@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data {
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struct clk *sample_clk;
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int default_sample_phase;
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int num_phases;
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+ bool internal_phase;
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};
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+/*
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+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
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+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
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+ */
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+static int rockchip_mmc_get_internal_phase(struct dw_mci *host, bool sample)
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+{
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+ unsigned long rate = clk_get_rate(host->ciu_clk);
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+ u32 raw_value;
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+ u16 degrees;
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+ u32 delay_num = 0;
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+
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+ /* Constant signal, no measurable phase shift */
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+ if (!rate)
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+ return 0;
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+
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+ if (sample)
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+ raw_value = mci_readl(host, TIMING_CON1);
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+ else
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+ raw_value = mci_readl(host, TIMING_CON0);
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+
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+ raw_value >>= ROCKCHIP_MMC_DEGREE_OFFSET;
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+ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
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+
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+ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
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+ /* degrees/delaynum * 1000000 */
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+ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
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+ 36 * (rate / 10000);
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+
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+ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
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+ delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
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+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
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+ }
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+
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+ return degrees % 360;
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+}
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+
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+static int rockchip_mmc_get_phase(struct dw_mci *host, bool sample)
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+{
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+ struct dw_mci_rockchip_priv_data *priv = host->priv;
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+ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk;
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+
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+ if (priv->internal_phase)
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+ return rockchip_mmc_get_internal_phase(host, sample);
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+ else
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+ return clk_get_phase(clock);
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+}
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+
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+static int rockchip_mmc_set_internal_phase(struct dw_mci *host, bool sample, int degrees)
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+{
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+ unsigned long rate = clk_get_rate(host->ciu_clk);
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+ u8 nineties, remainder;
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+ u8 delay_num;
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+ u32 raw_value;
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+ u32 delay;
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+
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+ /*
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+ * The below calculation is based on the output clock from
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+ * MMC host to the card, which expects the phase clock inherits
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+ * the clock rate from its parent, namely the output clock
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+ * provider of MMC host. However, things may go wrong if
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+ * (1) It is orphan.
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+ * (2) It is assigned to the wrong parent.
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+ *
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+ * This check help debug the case (1), which seems to be the
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+ * most likely problem we often face and which makes it difficult
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+ * for people to debug unstable mmc tuning results.
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+ */
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+ if (!rate) {
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+ dev_err(host->dev, "%s: invalid clk rate\n", __func__);
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+ return -EINVAL;
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+ }
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+
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+ nineties = degrees / 90;
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+ remainder = (degrees % 90);
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+
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+ /*
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+ * Due to the inexact nature of the "fine" delay, we might
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+ * actually go non-monotonic. We don't go _too_ monotonic
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+ * though, so we should be OK. Here are options of how we may
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+ * work:
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+ *
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+ * Ideally we end up with:
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+ * 1.0, 2.0, ..., 69.0, 70.0, ..., 89.0, 90.0
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+ *
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+ * On one extreme (if delay is actually 44ps):
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+ * .73, 1.5, ..., 50.6, 51.3, ..., 65.3, 90.0
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+ * The other (if delay is actually 77ps):
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+ * 1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
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+ *
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+ * It's possible we might make a delay that is up to 25
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+ * degrees off from what we think we're making. That's OK
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+ * though because we should be REALLY far from any bad range.
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+ */
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+
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+ /*
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+ * Convert to delay; do a little extra work to make sure we
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+ * don't overflow 32-bit / 64-bit numbers.
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+ */
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+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
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+ delay *= remainder;
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+ delay = DIV_ROUND_CLOSEST(delay,
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+ (rate / 1000) * 36 *
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+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
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+
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+ delay_num = (u8) min_t(u32, delay, 255);
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+
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+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
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+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
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+ raw_value |= nineties;
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+
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+ if (sample)
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+ mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1));
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+ else
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+ mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1));
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+
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+ dev_dbg(host->dev, "set %s_phase(%d) delay_nums=%u actual_degrees=%d\n",
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+ sample ? "sample" : "drv", degrees, delay_num,
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+ rockchip_mmc_get_phase(host, sample)
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+ );
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+
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+ return 0;
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+}
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+
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+static int rockchip_mmc_set_phase(struct dw_mci *host, bool sample, int degrees)
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+{
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+ struct dw_mci_rockchip_priv_data *priv = host->priv;
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+ struct clk *clock = sample ? priv->sample_clk : priv->drv_clk;
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+
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+ if (priv->internal_phase)
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+ return rockchip_mmc_set_internal_phase(host, sample, degrees);
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+ else
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+ return clk_set_phase(clock, degrees);
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+}
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+
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static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_rockchip_priv_data *priv = host->priv;
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@@ -64,7 +209,7 @@ static void dw_mci_rk3288_set_ios(struct
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/* Make sure we use phases which we can enumerate with */
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if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
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- clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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+ rockchip_mmc_set_phase(host, true, priv->default_sample_phase);
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/*
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* Set the drive phase offset based on speed mode to achieve hold times.
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@@ -127,7 +272,7 @@ static void dw_mci_rk3288_set_ios(struct
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break;
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}
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- clk_set_phase(priv->drv_clk, phase);
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+ rockchip_mmc_set_phase(host, false, phase);
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}
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}
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@@ -151,6 +296,7 @@ static int dw_mci_rk3288_execute_tuning(
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int longest_range_len = -1;
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int longest_range = -1;
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int middle_phase;
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+ int phase;
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if (IS_ERR(priv->sample_clk)) {
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dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
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@@ -164,8 +310,10 @@ static int dw_mci_rk3288_execute_tuning(
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/* Try each phase and extract good ranges */
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for (i = 0; i < priv->num_phases; ) {
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- clk_set_phase(priv->sample_clk,
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- TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
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+ rockchip_mmc_set_phase(host, true,
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+ TUNING_ITERATION_TO_PHASE(
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+ i,
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+ priv->num_phases));
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v = !mmc_send_tuning(mmc, opcode, NULL);
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@@ -211,7 +359,8 @@ static int dw_mci_rk3288_execute_tuning(
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}
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if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
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- clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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+ rockchip_mmc_set_phase(host, true, priv->default_sample_phase);
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+
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dev_info(host->dev, "All phases work, using default phase %d.",
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priv->default_sample_phase);
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goto free;
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@@ -248,12 +397,10 @@ static int dw_mci_rk3288_execute_tuning(
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middle_phase = ranges[longest_range].start + longest_range_len / 2;
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middle_phase %= priv->num_phases;
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- dev_info(host->dev, "Successfully tuned phase to %d\n",
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- TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
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+ phase = TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases);
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+ dev_info(host->dev, "Successfully tuned phase to %d\n", phase);
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- clk_set_phase(priv->sample_clk,
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- TUNING_ITERATION_TO_PHASE(middle_phase,
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- priv->num_phases));
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+ rockchip_mmc_set_phase(host, true, phase);
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free:
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kfree(ranges);
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@@ -287,6 +434,8 @@ static int dw_mci_rk3288_parse_dt(struct
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host->priv = priv;
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+ priv->internal_phase = false;
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+
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return 0;
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}
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