mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
81 lines
2.3 KiB
Diff
81 lines
2.3 KiB
Diff
From 8b579881de295d49a75f6312547f7813b1551a83 Mon Sep 17 00:00:00 2001
|
|
From: Detlev Casanova <detlev.casanova@collabora.com>
|
|
Date: Thu, 29 Aug 2024 16:20:47 -0400
|
|
Subject: [PATCH] pmdomain: rockchip: Add gating support
|
|
|
|
Some rockchip SoC need to ungate power domains before their power status
|
|
can be changed.
|
|
|
|
Each power domain has a gate mask that is set to 1 to ungate it when
|
|
manipulating power status, then set back to 0 to gate it again.
|
|
|
|
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
|
|
Link: https://lore.kernel.org/r/20240829202732.75961-2-detlev.casanova@collabora.com
|
|
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
|
---
|
|
drivers/pmdomain/rockchip/pm-domains.c | 25 +++++++++++++++++++++++++
|
|
1 file changed, 25 insertions(+)
|
|
|
|
--- a/drivers/pmdomain/rockchip/pm-domains.c
|
|
+++ b/drivers/pmdomain/rockchip/pm-domains.c
|
|
@@ -44,6 +44,7 @@ struct rockchip_domain_info {
|
|
bool active_wakeup;
|
|
int pwr_w_mask;
|
|
int req_w_mask;
|
|
+ int clk_ungate_mask;
|
|
int mem_status_mask;
|
|
int repair_status_mask;
|
|
u32 pwr_offset;
|
|
@@ -61,6 +62,7 @@ struct rockchip_pmu_info {
|
|
u32 chain_status_offset;
|
|
u32 mem_status_offset;
|
|
u32 repair_status_offset;
|
|
+ u32 clk_ungate_offset;
|
|
|
|
u32 core_pwrcnt_offset;
|
|
u32 gpu_pwrcnt_offset;
|
|
@@ -301,6 +303,26 @@ static unsigned int rockchip_pmu_read_ac
|
|
return val;
|
|
}
|
|
|
|
+static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
|
|
+{
|
|
+ const struct rockchip_domain_info *pd_info = pd->info;
|
|
+ struct rockchip_pmu *pmu = pd->pmu;
|
|
+ unsigned int val;
|
|
+ int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
|
|
+
|
|
+ if (!pd_info->clk_ungate_mask)
|
|
+ return 0;
|
|
+
|
|
+ if (!pmu->info->clk_ungate_offset)
|
|
+ return 0;
|
|
+
|
|
+ val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
|
|
+ clk_ungate_w_mask;
|
|
+ regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
|
|
bool idle)
|
|
{
|
|
@@ -541,6 +563,8 @@ static int rockchip_pd_power(struct rock
|
|
return ret;
|
|
}
|
|
|
|
+ rockchip_pmu_ungate_clk(pd, true);
|
|
+
|
|
if (!power_on) {
|
|
rockchip_pmu_save_qos(pd);
|
|
|
|
@@ -557,6 +581,7 @@ static int rockchip_pd_power(struct rock
|
|
rockchip_pmu_restore_qos(pd);
|
|
}
|
|
|
|
+ rockchip_pmu_ungate_clk(pd, false);
|
|
clk_bulk_disable(pd->num_clks, pd->clks);
|
|
}
|
|
|