mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-06-20 08:05:29 +08:00
67 lines
2.7 KiB
Diff
67 lines
2.7 KiB
Diff
--- a/drivers/clk/qcom/gcc-ipq6018.c
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+++ b/drivers/clk/qcom/gcc-ipq6018.c
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@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data
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gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy1_gcc_rx_clk" },
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- { .fw_name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data
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gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy1_gcc_tx_clk" },
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- { .fw_name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
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@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo" },
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- { .fw_name = "uniphy0_gcc_tx_clk" },
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- { .fw_name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .fw_name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
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