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53 lines
1.7 KiB
Diff
53 lines
1.7 KiB
Diff
From 36299757129c897ef8c7ace6981070d367d89f89 Mon Sep 17 00:00:00 2001
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From: Detlev Casanova <detlev.casanova@collabora.com>
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Date: Fri, 28 Feb 2025 09:50:47 -0500
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Subject: [PATCH] arm64: dts: rockchip: Add SFC nodes for rk3576
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The rk3576 SoC has 2 SFC cores that provide FSPI functions.
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Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
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Link: https://lore.kernel.org/r/20250228145304.581349-2-detlev.casanova@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
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1 file changed, 22 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1334,6 +1334,17 @@ gmac1_mtl_tx_setup: tx-queues-config {
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};
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};
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+ sfc1: spi@2a300000 {
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+ compatible = "rockchip,sfc";
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+ reg = <0x0 0x2a300000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
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+ clock-names = "clk_sfc", "hclk_sfc";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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sdmmc: mmc@2a310000 {
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compatible = "rockchip,rk3576-dw-mshc";
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reg = <0x0 0x2a310000 0x0 0x4000>;
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@@ -1373,6 +1384,17 @@ sdhci: mmc@2a330000 {
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status = "disabled";
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};
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+ sfc0: spi@2a340000 {
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+ compatible = "rockchip,sfc";
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+ reg = <0x0 0x2a340000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
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+ clock-names = "clk_sfc", "hclk_sfc";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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otp: otp@2a580000 {
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compatible = "rockchip,rk3576-otp";
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reg = <0x0 0x2a580000 0x0 0x400>;
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