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48 lines
1.3 KiB
Diff
48 lines
1.3 KiB
Diff
From d2cdc83fb2c7360856e598810b88211d815fc851 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:12 +0800
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Subject: [PATCH 2/3] arm64: dts: qcom: ipq5018: add mdio node
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The IPQ5018 SoC contains two MDIO controllers. MDIO0 is used to control
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its internal GE Phy, while MDIO1 is wired to external PHYs/switch.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 20 ++++++++++++++++++++
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1 file changed, 20 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -188,6 +188,30 @@
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status = "disabled";
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};
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+ mdio0: mdio@88000 {
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+ compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio";
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+ reg = <0x00088000 0x64>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ clocks = <&gcc GCC_MDIO0_AHB_CLK>;
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+ clock-names = "gcc_mdio_ahb_clk";
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+
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+ status = "disabled";
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+ };
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+
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+ mdio1: mdio@90000 {
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+ compatible = "qcom,ipq5018-mdio";
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+ reg = <0x00090000 0x64>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ clocks = <&gcc GCC_MDIO1_AHB_CLK>;
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+ clock-names = "gcc_mdio_ahb_clk";
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+
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+ status = "disabled";
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+ };
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+
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cmn_pll: clock-controller@9b000 {
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compatible = "qcom,ipq9574-cmn-pll";
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reg = <0x0009b000 0x800>,
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