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177 lines
4.6 KiB
Diff
177 lines
4.6 KiB
Diff
From 6f8c1ed25809181c187a59b1caaa1521756924bf Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Tue, 22 Oct 2024 17:47:26 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq: change labels to lower-case
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DTS coding style expects labels to be lowercase. No functional impact.
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Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-1-0505bc7d2c56@linaro.org
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +++---
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arch/arm64/boot/dts/qcom/ipq5332.dtsi | 18 +++++-----
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 26 +++++++-------
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 18 +++++-----
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 50 +++++++++++++--------------
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5 files changed, 61 insertions(+), 61 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -31,27 +31,27 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- CPU0: cpu@0 {
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+ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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- CPU1: cpu@1 {
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+ cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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- L2_0: l2-cache {
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+ l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x80000>;
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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@@ -34,12 +34,12 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- CPU0: cpu@0 {
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+ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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@@ -47,12 +47,12 @@
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#cooling-cells = <2>;
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};
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- CPU1: cpu@1 {
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+ cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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@@ -60,12 +60,12 @@
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#cooling-cells = <2>;
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};
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- CPU2: cpu@2 {
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+ cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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@@ -73,12 +73,12 @@
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#cooling-cells = <2>;
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};
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- CPU3: cpu@3 {
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+ cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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clock-names = "cpu";
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operating-points-v2 = <&cpu_opp_table>;
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@@ -86,7 +86,7 @@
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#cooling-cells = <2>;
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};
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- L2_0: l2-cache {
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+ l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -32,39 +32,39 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- CPU0: cpu@0 {
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+ cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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enable-method = "psci";
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};
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- CPU1: cpu@1 {
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+ cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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};
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- CPU2: cpu@2 {
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+ cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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};
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- CPU3: cpu@3 {
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+ cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x3>;
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- next-level-cache = <&L2_0>;
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+ next-level-cache = <&l2_0>;
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};
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- L2_0: l2-cache {
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+ l2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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