mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 14:23:38 +00:00
30 lines
1.3 KiB
Diff
30 lines
1.3 KiB
Diff
--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -171,6 +171,7 @@ void __init ralink_clk_init(void)
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u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
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u32 pll, prediv, fbdiv;
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u32 xtal_clk, cpu_clk, bus_clk;
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+ u32 target_fbdiv, target_pll;
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const static u32 prediv_tbl[] = {0, 1, 2, 2};
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syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
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@@ -198,6 +199,18 @@ void __init ralink_clk_init(void)
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pll = rt_memc_r32(MEMC_REG_CPU_PLL);
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fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
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prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
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+ /* When using the PLL, this code will overclock the CPU */
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+#define MT7621A_TARGET_CLOCK_HZ 1000000000
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+ target_fbdiv = (MT7621A_TARGET_CLOCK_HZ * ffiv) / ffrac;
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+ target_fbdiv = target_fbdiv << prediv_tbl[prediv];
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+ target_fbdiv = (target_fbdiv / xtal_clk) - 1;
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+ target_pll = pll & ~(CPU_PLL_FBDIV_MASK << CPU_PLL_FBDIV_SHIFT);
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+ target_pll = target_pll | (target_fbdiv << CPU_PLL_FBDIV_SHIFT);
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+ pr_info("CPU Overclock PLL: 0x%x\n", target_pll);
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+ rt_memc_w32(target_pll, MEMC_REG_CPU_PLL);
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+ pll = rt_memc_r32(MEMC_REG_CPU_PLL);
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+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
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+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
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cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
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break;
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default:
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