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719b7258f6
Replace the existing SPI NAND controller patches with the latest v14 set that is pending upstream, and include Ansuels patch that fixes it. Bindings patch is removed as there is no point carrying it in OpenWrt. Signed-off-by: Robert Marko <robimarko@gmail.com>
53 lines
1.5 KiB
Diff
53 lines
1.5 KiB
Diff
From c2019f64539dd24e6e0da3cea2219d6f9e6b03e4 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:11 +0800
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add SPI nand node
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Add SPI NAND support for IPQ5018 SoC.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 40 +++++++++++++++++++++++++++
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1 file changed, 40 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -461,6 +461,36 @@
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status = "disabled";
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};
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+ qpic_bam: dma@7984000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x07984000 0x1c000>;
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+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ status = "disabled";
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+ };
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+
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+ qpic_nand: qpic-nand@79b0000 {
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+ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";
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+ reg = <0x079b0000 0x10000>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+
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+ dmas = <&qpic_bam 0>,
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+ <&qpic_bam 1>,
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+ <&qpic_bam 2>,
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+ <&qpic_bam 3>;
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+ dma-names = "tx", "rx", "cmd", "status";
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+
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+ status = "disabled";
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+ };
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+
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usb: usb@8af8800 {
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compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
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reg = <0x08af8800 0x400>;
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