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719b7258f6
Replace the existing SPI NAND controller patches with the latest v14 set that is pending upstream, and include Ansuels patch that fixes it. Bindings patch is removed as there is no point carrying it in OpenWrt. Signed-off-by: Robert Marko <robimarko@gmail.com>
126 lines
3.9 KiB
Diff
126 lines
3.9 KiB
Diff
From 8716f3c03d9f71ed0bd12a26f6e9d1e85cff0d12 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Thu, 30 Jan 2025 00:27:22 +0100
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Subject: [PATCH 1/2] spi: spi-qpic: fix broken driver with SPINAND_SET_FEATURE
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command
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The driver always return probe error with SPINAND_SET_FEATURE command:
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spi-nand: probe of spi0.0 failed with error -1207959538
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The error doesn't match any expected negative error but instead seems to
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be an u32 converted to an int. Investigating the entire codeflow I
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reached the culprit: qcom_spi_cmd_mapping.
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Such function can return -EOPNOTSUPP or the cmd to run. Problem is that
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in the specific context of SPINAND_SET_FEATURE, BIT(31) is set that in
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the context of an integer, it gets treated as a negative value.
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To correctly handle this, rework the function to return 0 or a "correct"
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negative error and pass a pointer to store the cmd.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/spi/spi-qpic-snand.c | 40 +++++++++++++++++-------------------
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1 file changed, 19 insertions(+), 21 deletions(-)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -1200,64 +1200,64 @@ static int qcom_spi_program_execute(stru
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return 0;
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}
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-static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
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+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
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+ u32 *cmd)
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{
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- int cmd = 0x0;
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-
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switch (opcode) {
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case SPINAND_RESET:
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- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
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+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
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break;
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case SPINAND_READID:
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- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
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+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
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break;
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case SPINAND_GET_FEATURE:
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- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
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+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
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break;
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case SPINAND_SET_FEATURE:
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- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
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+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
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QPIC_SET_FEATURE);
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break;
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case SPINAND_READ:
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if (snandc->qspi->raw_rw) {
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- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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SPI_WP | SPI_HOLD | OP_PAGE_READ);
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} else {
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- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
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}
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break;
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case SPINAND_ERASE:
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- cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
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+ *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
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SPI_HOLD | SPI_TRANSFER_MODE_x1;
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break;
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case SPINAND_WRITE_EN:
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- cmd = SPINAND_WRITE_EN;
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+ *cmd = SPINAND_WRITE_EN;
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break;
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case SPINAND_PROGRAM_EXECUTE:
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- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
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SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
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break;
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case SPINAND_PROGRAM_LOAD:
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- cmd = SPINAND_PROGRAM_LOAD;
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+ *cmd = SPINAND_PROGRAM_LOAD;
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break;
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default:
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dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
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return -EOPNOTSUPP;
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}
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- return cmd;
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+ return 0;
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}
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static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
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const struct spi_mem_op *op)
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{
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- int cmd;
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+ u32 cmd;
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+ int ret;
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- cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
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- if (cmd < 0)
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- return cmd;
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+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
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+ if (ret < 0)
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+ return ret;
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if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
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snandc->qspi->data_buf = (u8 *)op->data.buf.out;
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@@ -1272,12 +1272,10 @@ static int qcom_spi_send_cmdaddr(struct
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u32 cmd;
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int ret, opcode;
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- ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
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+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
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if (ret < 0)
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return ret;
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- cmd = ret;
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-
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s_op.cmd_reg = cmd;
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s_op.addr1_reg = op->addr.val;
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s_op.addr2_reg = 0;
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