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d5b41ff34f
Add patch to fix Qcom SNAND driver and move the SNAND patches to backports directory as they are shared between qualcommax and qualcommbe target. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Robert Marko <robimarko@gmail.com>
65 lines
2.8 KiB
Diff
65 lines
2.8 KiB
Diff
From 9d4ffbcfde283f2a87ea45128ddf7e6651facdd9 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 7 Feb 2025 20:42:38 +0100
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Subject: [PATCH] mtd: rawnand: qcom: fix broken config in
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qcom_param_page_type_exec
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Fix broken config in qcom_param_page_type_exec caused by copy-paste error
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from commit 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")
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In qcom_param_page_type_exec the value needs to be set to
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nandc->regs->cfg0 instead of host->cfg0. This wrong configuration caused
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the Qcom NANDC driver to malfunction on any device that makes use of it
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(IPQ806x, IPQ40xx, IPQ807x, IPQ60xx) with the following error:
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[ 0.885369] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xaa
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[ 0.885909] nand: Micron NAND 256MiB 1,8V 8-bit
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[ 0.892499] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
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[ 0.896823] nand: ECC (step, strength) = (512, 8) does not fit in OOB
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[ 0.896836] qcom-nandc 79b0000.nand-controller: No valid ECC settings possible
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[ 0.910996] bam-dma-engine 7984000.dma-controller: Cannot free busy channel
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[ 0.918070] qcom-nandc: probe of 79b0000.nand-controller failed with error -28
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Restore original configuration fix the problem and makes the driver work
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again.
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Cc: stable@vger.kernel.org
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Fixes: 0c08080fd71c ("mtd: rawnand: qcom: use FIELD_PREP and GENMASK")
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 24 ++++++++++++------------
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1 file changed, 12 insertions(+), 12 deletions(-)
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -1881,18 +1881,18 @@ static int qcom_param_page_type_exec(str
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nandc->regs->addr0 = 0;
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nandc->regs->addr1 = 0;
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- host->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
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- FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
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- FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
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- FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
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+ nandc->regs->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, 0) |
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+ FIELD_PREP(UD_SIZE_BYTES_MASK, 512) |
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+ FIELD_PREP(NUM_ADDR_CYCLES_MASK, 5) |
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+ FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
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- host->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
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- FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
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- FIELD_PREP(CS_ACTIVE_BSY, 0) |
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- FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
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- FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
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- FIELD_PREP(WIDE_FLASH, 0) |
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- FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
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+ nandc->regs->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 7) |
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+ FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
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+ FIELD_PREP(CS_ACTIVE_BSY, 0) |
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+ FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
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+ FIELD_PREP(WR_RD_BSY_GAP_MASK, 2) |
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+ FIELD_PREP(WIDE_FLASH, 0) |
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+ FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
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if (!nandc->props->qpic_version2)
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nandc->regs->ecc_buf_cfg = cpu_to_le32(ECC_CFG_ECC_DISABLE);
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