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50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Mon, 4 Sep 2017 15:00:10 +0530
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Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq
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If the parent clock rate is greater than unsigned long max
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divided by 2 then the integer overflow is happening while
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calculating the clock rate. Since RCG2 uses half integer
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dividers, the clock rate is first being multiplied by 2
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followed by division and this multiplication leads to
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overflow.
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Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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(cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430)
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e
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---
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drivers/clk/qcom/clk-rcg2.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -145,18 +145,18 @@ static int clk_rcg2_set_parent(struct cl
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* hid_div n
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*/
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static unsigned long
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-calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
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+calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div)
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{
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+ u64 rate = parent_rate;
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+
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if (hid_div) {
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rate *= 2;
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- rate /= hid_div + 1;
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+ do_div(rate, hid_div + 1);
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}
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if (mode) {
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- u64 tmp = rate;
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- tmp *= m;
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- do_div(tmp, n);
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- rate = tmp;
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+ rate *= m;
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+ do_div(rate, n);
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}
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return rate;
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