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202 lines
6.4 KiB
Diff
202 lines
6.4 KiB
Diff
From 5dc9d1a55e953d9059ecbdd8fe6ec81e9edd349e Mon Sep 17 00:00:00 2001
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From: Baochen Qiang <quic_bqiang@quicinc.com>
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Date: Tue, 9 Jan 2024 10:13:36 +0800
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Subject: [PATCH] wifi: ath11k: add support for QCA2066
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QCA2066 is a PCI based DBS device. It is very similar to WCN6855
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overall: they share the same PCI device ID, the same major and
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minor version numbers, the same register address, and same HAL
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descriptors etc. The most significant difference is that QCA2066
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supports 3-antenna configuration while WCN6855 does not. To differentiate
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them, subversion numbers are used. Currently four numbers are used
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by QCA2066: 0x1019A0E1, 0x1019B0E1, 0x1019C0E1 and 0x1019D0E1.
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Tested-on: QCA2066 hw2.1 PCI WLAN.HSP.1.1-03737-QCAHSPSWPL_V2_SILICONZ_CE-1
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Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3
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Signed-off-by: Baochen Qiang <quic_bqiang@quicinc.com>
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Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com>
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Link: https://msgid.link/20240109021336.4143-3-quic_bqiang@quicinc.com
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---
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drivers/net/wireless/ath/ath11k/core.c | 86 ++++++++++++++++++++++++++
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drivers/net/wireless/ath/ath11k/core.h | 1 +
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drivers/net/wireless/ath/ath11k/mhi.c | 1 +
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drivers/net/wireless/ath/ath11k/pci.c | 17 ++++-
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drivers/net/wireless/ath/ath11k/pcic.c | 11 ++++
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5 files changed, 115 insertions(+), 1 deletion(-)
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--- a/drivers/net/wireless/ath/ath11k/core.c
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+++ b/drivers/net/wireless/ath/ath11k/core.c
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@@ -702,6 +702,91 @@ static const struct ath11k_hw_params ath
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.smp2p_wow_exit = false,
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.support_fw_mac_sequence = false,
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},
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+ {
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+ .name = "qca2066 hw2.1",
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+ .hw_rev = ATH11K_HW_QCA2066_HW21,
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+ .fw = {
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+ .dir = "QCA2066/hw2.1",
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+ .board_size = 256 * 1024,
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+ .cal_offset = 128 * 1024,
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+ },
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+ .max_radios = 3,
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+ .bdf_addr = 0x4B0C0000,
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+ .hw_ops = &wcn6855_ops,
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+ .ring_mask = &ath11k_hw_ring_mask_qca6390,
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+ .internal_sleep_clock = true,
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+ .regs = &wcn6855_regs,
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+ .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390,
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+ .host_ce_config = ath11k_host_ce_config_qca6390,
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+ .ce_count = 9,
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+ .target_ce_config = ath11k_target_ce_config_wlan_qca6390,
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+ .target_ce_count = 9,
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+ .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
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+ .svc_to_ce_map_len = 14,
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+ .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074,
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+ .single_pdev_only = true,
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+ .rxdma1_enable = false,
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+ .num_rxmda_per_pdev = 2,
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+ .rx_mac_buf_ring = true,
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+ .vdev_start_delay = true,
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+ .htt_peer_map_v2 = false,
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+
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+ .spectral = {
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+ .fft_sz = 0,
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+ .fft_pad_sz = 0,
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+ .summary_pad_sz = 0,
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+ .fft_hdr_len = 0,
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+ .max_fft_bins = 0,
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+ .fragment_160mhz = false,
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+ },
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+
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+ .interface_modes = BIT(NL80211_IFTYPE_STATION) |
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+ BIT(NL80211_IFTYPE_AP),
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+ .supports_monitor = false,
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+ .full_monitor_mode = false,
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+ .supports_shadow_regs = true,
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+ .idle_ps = true,
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+ .supports_sta_ps = true,
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+ .coldboot_cal_mm = false,
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+ .coldboot_cal_ftm = false,
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+ .cbcal_restart_fw = false,
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+ .fw_mem_mode = 0,
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+ .num_vdevs = 2 + 1,
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+ .num_peers = 512,
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+ .supports_suspend = true,
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+ .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855),
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+ .supports_regdb = true,
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+ .fix_l1ss = false,
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+ .credit_flow = true,
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+ .max_tx_ring = DP_TCL_NUM_RING_MAX_QCA6390,
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+ .hal_params = &ath11k_hw_hal_params_qca6390,
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+ .supports_dynamic_smps_6ghz = false,
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+ .alloc_cacheable_memory = false,
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+ .supports_rssi_stats = true,
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+ .fw_wmi_diag_event = true,
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+ .current_cc_support = true,
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+ .dbr_debug_support = false,
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+ .global_reset = true,
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+ .bios_sar_capa = &ath11k_hw_sar_capa_wcn6855,
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+ .m3_fw_support = true,
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+ .fixed_bdf_addr = false,
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+ .fixed_mem_region = false,
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+ .static_window_map = false,
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+ .hybrid_bus_type = false,
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+ .fixed_fw_mem = false,
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+ .support_off_channel_tx = true,
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+ .supports_multi_bssid = true,
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+
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+ .sram_dump = {
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+ .start = 0x01400000,
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+ .end = 0x0177ffff,
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+ },
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+
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+ .tcl_ring_retry = true,
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+ .tx_ring_size = DP_TCL_DATA_RING_SIZE,
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+ .smp2p_wow_exit = false,
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+ .support_fw_mac_sequence = true,
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+ },
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};
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static inline struct ath11k_pdev *ath11k_core_get_single_pdev(struct ath11k_base *ab)
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--- a/drivers/net/wireless/ath/ath11k/core.h
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+++ b/drivers/net/wireless/ath/ath11k/core.h
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@@ -144,6 +144,7 @@ enum ath11k_hw_rev {
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ATH11K_HW_WCN6855_HW21,
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ATH11K_HW_WCN6750_HW10,
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ATH11K_HW_IPQ5018_HW10,
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+ ATH11K_HW_QCA2066_HW21,
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};
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enum ath11k_firmware_mode {
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--- a/drivers/net/wireless/ath/ath11k/mhi.c
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+++ b/drivers/net/wireless/ath/ath11k/mhi.c
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@@ -437,6 +437,7 @@ int ath11k_mhi_register(struct ath11k_pc
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case ATH11K_HW_QCA6390_HW20:
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case ATH11K_HW_WCN6855_HW20:
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case ATH11K_HW_WCN6855_HW21:
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+ case ATH11K_HW_QCA2066_HW21:
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ath11k_mhi_config = &ath11k_mhi_config_qca6390;
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break;
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default:
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--- a/drivers/net/wireless/ath/ath11k/pci.c
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+++ b/drivers/net/wireless/ath/ath11k/pci.c
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@@ -28,6 +28,8 @@
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#define QCN9074_DEVICE_ID 0x1104
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#define WCN6855_DEVICE_ID 0x1103
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+#define TCSR_SOC_HW_SUB_VER 0x1910010
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+
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static const struct pci_device_id ath11k_pci_id_table[] = {
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{ PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
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{ PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
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@@ -730,6 +732,7 @@ static int ath11k_pci_probe(struct pci_d
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struct ath11k_pci *ab_pci;
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u32 soc_hw_version_major, soc_hw_version_minor, addr;
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int ret;
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+ u32 sub_version;
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ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
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@@ -820,7 +823,19 @@ static int ath11k_pci_probe(struct pci_d
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break;
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case 0x10:
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case 0x11:
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- ab->hw_rev = ATH11K_HW_WCN6855_HW21;
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+ sub_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_SUB_VER);
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+ ath11k_dbg(ab, ATH11K_DBG_PCI, "sub_version 0x%x\n",
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+ sub_version);
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+ switch (sub_version) {
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+ case 0x1019A0E1:
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+ case 0x1019B0E1:
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+ case 0x1019C0E1:
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+ case 0x1019D0E1:
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+ ab->hw_rev = ATH11K_HW_QCA2066_HW21;
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+ break;
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+ default:
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+ ab->hw_rev = ATH11K_HW_WCN6855_HW21;
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+ }
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break;
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default:
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goto unsupported_wcn6855_soc;
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--- a/drivers/net/wireless/ath/ath11k/pcic.c
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+++ b/drivers/net/wireless/ath/ath11k/pcic.c
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@@ -115,6 +115,17 @@ static const struct ath11k_msi_config at
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},
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.hw_rev = ATH11K_HW_WCN6750_HW10,
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},
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+ {
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+ .total_vectors = 32,
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+ .total_users = 4,
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+ .users = (struct ath11k_msi_user[]) {
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+ { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
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+ { .name = "CE", .num_vectors = 10, .base_vector = 3 },
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+ { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
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+ { .name = "DP", .num_vectors = 18, .base_vector = 14 },
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+ },
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+ .hw_rev = ATH11K_HW_QCA2066_HW21,
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+ },
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};
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int ath11k_pcic_init_msi_config(struct ath11k_base *ab)
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