lede/target/linux/mediatek/dts/mt7986a-tplink-tl-xtr8488.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;
#include "mt7986a-tplink-tl-xdr-common.dtsi"

/ {
	model = "TP-Link TL-XTR8488";
	compatible = "tplink,tl-xtr8488";

	keys {
		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 15 GPIO_ACTIVE_LOW>;
		};

		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 16 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		turbo {
			label = "green:turbo";
			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
		};
	};
};

&eth {
	/delete-node/ mdio-bus;

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		phy5: phy@5 {
			compatible = "ethernet-phy-ieee802.3-c45";
			reg = <5>;
			realtek,aldps-enable;
			realtek,led-link-select = <0xa7 0x0 0x0>;
		};

		phy7: phy@7 {
			compatible = "ethernet-phy-ieee802.3-c45";
			reg = <7>;
			realtek,aldps-enable;
			realtek,led-link-select = <0xa7 0x0 0x0>;
		};

		switch: switch@0 {
			compatible = "mediatek,mt7531";
			reg = <31>;
			reset-gpios = <&pio 6 GPIO_ACTIVE_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&pio>;
			interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan4";
		};

		port@1 {
			reg = <1>;
			label = "lan3";
		};

		port@2 {
			reg = <2>;
			label = "lan2";
		};

		port@3 {
			reg = <3>;
			label = "lan1";
		};

		port@5 {
			reg = <5>;
			label = "lan5";
			phy-handle = <&phy5>;
			phy-mode = "2500base-x";
		};

		port@6 {
			reg = <6>;
			label = "cpu";
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&spi0 {
	flash@0 {
		/delete-node/ partitions;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "bl2";
				reg = <0x000000 0x0100000>;
				read-only;
			};

			config: partition@100000 {
				label = "config";
				reg = <0x100000 0x0040000>;
				read-only;
			};

			factory: partition@140000 {
				label = "factory";
				reg = <0x140000 0x0040000>;
				read-only;
			};

			partition@180000 {
				label = "reserved";
				reg = <0x180000 0x0180000>;
				read-only;
			};

			partition@300000 {
				label = "u-boot-env";
				reg = <0x300000 0x0080000>;
			};

			partition@380000 {
				label = "fip";
				reg = <0x380000 0x0200000>;
				read-only;
			};

			partition@580000 {
				label = "ubi";
				reg = <0x580000 0x7800000>;
			};
		};
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pcie_pins>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;

		wifi@0,0 {
			compatible = "mediatek,mt76";
			reg = <0x0000 0 0 0 0>;
			mediatek,mtd-eeprom = <&factory 0x1000>;
			ieee80211-freq-limit = <5470000 5875000>;

			nvmem-cells = <&macaddr_config_1c 3>;
			nvmem-cell-names = "mac-address";
		};
	};
};

&pcie_phy {
	status = "okay";
};

&pio {
	pcie_pins: pcie-pins {
		mux {
			function = "pcie";
			groups = "pcie_clk", "pcie_wake", "pcie_pereset";
		};
	};

	wf_2g_5g_pins: wf_2g_5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <4>;
		};
	};
};

&wifi {
	pinctrl-names = "default";
	pinctrl-0 = <&wf_2g_5g_pins>;
	ieee80211-freq-limit = <2400000 2500000>, <5170000 5350000>;
};

&config {
	nvmem-layout {
		compatible = "fixed-layout";
		#address-cells = <1>;
		#size-cells = <1>;

		macaddr_config_1c: macaddr@1c {
			compatible = "mac-base";
			reg = <0x1c 0x6>;
			#nvmem-cell-cells = <1>;
		};
	};
};