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https://github.com/coolsnowwolf/lede.git
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61 lines
2.4 KiB
Diff
61 lines
2.4 KiB
Diff
From 14ad41c74f6be0bfaf5202b7e49254e2482da56f Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Mon, 4 Oct 2021 12:03:33 +0100
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Subject: [PATCH] net: ethernet: use phylink_set_10g_modes()
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Update three drivers to use the new phylink_set_10g_modes() helper:
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Cadence macb, Freescale DPAA2 and Marvell PP2.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/cadence/macb_main.c | 7 +------
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drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 7 +------
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drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 +------
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3 files changed, 3 insertions(+), 18 deletions(-)
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--- a/drivers/net/ethernet/cadence/macb_main.c
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+++ b/drivers/net/ethernet/cadence/macb_main.c
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@@ -548,13 +548,8 @@ static void macb_validate(struct phylink
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if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
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(state->interface == PHY_INTERFACE_MODE_NA ||
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state->interface == PHY_INTERFACE_MODE_10GBASER)) {
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- phylink_set(mask, 10000baseCR_Full);
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- phylink_set(mask, 10000baseER_Full);
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+ phylink_set_10g_modes(mask);
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phylink_set(mask, 10000baseKR_Full);
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- phylink_set(mask, 10000baseLR_Full);
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- phylink_set(mask, 10000baseLRM_Full);
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- phylink_set(mask, 10000baseSR_Full);
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- phylink_set(mask, 10000baseT_Full);
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if (state->interface != PHY_INTERFACE_MODE_NA)
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goto out;
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}
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--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
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+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
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@@ -139,7 +139,7 @@ static void dpaa2_mac_validate(struct ph
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case PHY_INTERFACE_MODE_NA:
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_USXGMII:
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- phylink_set(mask, 10000baseT_Full);
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+ phylink_set_10g_modes(mask);
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if (state->interface == PHY_INTERFACE_MODE_10GBASER)
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break;
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phylink_set(mask, 5000baseT_Full);
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--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
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+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
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@@ -6335,12 +6335,7 @@ static void mvpp2_phylink_validate(struc
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case PHY_INTERFACE_MODE_XAUI:
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case PHY_INTERFACE_MODE_NA:
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if (mvpp2_port_supports_xlg(port)) {
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- phylink_set(mask, 10000baseT_Full);
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- phylink_set(mask, 10000baseCR_Full);
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- phylink_set(mask, 10000baseSR_Full);
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- phylink_set(mask, 10000baseLR_Full);
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- phylink_set(mask, 10000baseLRM_Full);
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- phylink_set(mask, 10000baseER_Full);
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+ phylink_set_10g_modes(mask);
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phylink_set(mask, 10000baseKR_Full);
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}
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if (state->interface != PHY_INTERFACE_MODE_NA)
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