mirror of
https://github.com/coolsnowwolf/lede.git
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124 lines
3.3 KiB
Diff
124 lines
3.3 KiB
Diff
From 62ff79396d8d4137b65195fcd20e3010b96b0902 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Fri, 8 Apr 2022 13:22:30 +0200
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Subject: [PATCH 41/50] arm64: dts: rockchip: rk356x: Add VOP2 nodes
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The VOP2 is the display output controller on the RK3568. Add the node
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for it to the dtsi file along with the required display-subsystem node
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and the iommu node.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Acked-by: Rob Herring <robh@kernel.org>
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---
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arch/arm64/boot/dts/rockchip/rk3566.dtsi | 4 ++
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 51 ++++++++++++++++++++++++
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include/dt-bindings/soc/rockchip,vop2.h | 14 +++++++
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4 files changed, 73 insertions(+)
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create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
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--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
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@@ -29,3 +29,7 @@
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extcon = <&usb2phy0>;
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maximum-speed = "high-speed";
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};
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+
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+&vop {
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+ compatible = "rockchip,rk3566-vop";
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -137,3 +137,7 @@
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phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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+
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+&vop {
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+ compatible = "rockchip,rk3568-vop";
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -129,6 +129,11 @@
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};
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};
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+ display_subsystem: display-subsystem {
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+ compatible = "rockchip,display-subsystem";
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+ ports = <&vop_out>;
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+ };
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+
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firmware {
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scmi: scmi {
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compatible = "arm,scmi-smc";
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@@ -632,6 +637,52 @@
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};
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};
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+ vop: vop@fe040000 {
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+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
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+ reg-names = "regs", "gamma_lut";
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+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
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+ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
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+ clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
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+ iommus = <&vop_mmu>;
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+ power-domains = <&power RK3568_PD_VO>;
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+ rockchip,grf = <&grf>;
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+ status = "disabled";
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+
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+ vop_out: ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ vp0: port@0 {
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ vp1: port@1 {
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+ reg = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ vp2: port@2 {
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+ reg = <2>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+ };
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+ };
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+
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+ vop_mmu: iommu@fe043e00 {
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+ compatible = "rockchip,rk3568-iommu";
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+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
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+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
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+ clock-names = "aclk", "iface";
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+ #iommu-cells = <0>;
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+ status = "disabled";
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+ };
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+
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qos_gpu: qos@fe128000 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe128000 0x0 0x20>;
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--- /dev/null
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+++ b/include/dt-bindings/soc/rockchip,vop2.h
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@@ -0,0 +1,14 @@
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+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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+
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+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
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+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
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+
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+#define ROCKCHIP_VOP2_EP_RGB0 1
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+#define ROCKCHIP_VOP2_EP_HDMI0 2
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+#define ROCKCHIP_VOP2_EP_EDP0 3
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+#define ROCKCHIP_VOP2_EP_MIPI0 4
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+#define ROCKCHIP_VOP2_EP_LVDS0 5
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+#define ROCKCHIP_VOP2_EP_MIPI1 6
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+#define ROCKCHIP_VOP2_EP_LVDS1 7
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+
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+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
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