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https://github.com/coolsnowwolf/lede.git
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86 lines
2.8 KiB
Diff
86 lines
2.8 KiB
Diff
From ac7d452ab34962172f64ad1ecf244b42fdb4bccf Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Fri, 8 Apr 2022 13:22:26 +0200
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Subject: [PATCH 37/50] drm/rockchip: dw_hdmi: drop mode_valid hook
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The driver checks if the pixel clock of the given mode matches an entry
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in the mpll config table. The frequencies in the mpll table are meant as
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a frequency range up to which the entry works, not as a frequency that
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must match the pixel clock. The downstream Kernel also does not have
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this check, so drop it to allow for more display resolutions.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 ---------------------
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1 file changed, 25 deletions(-)
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -248,26 +248,6 @@ static int rockchip_hdmi_parse_dt(struct
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return 0;
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}
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-static enum drm_mode_status
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-dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data,
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- const struct drm_display_info *info,
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- const struct drm_display_mode *mode)
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-{
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- const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg;
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- int pclk = mode->clock * 1000;
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- bool valid = false;
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- int i;
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-
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- for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
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- if (pclk == mpll_cfg[i].mpixelclock) {
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- valid = true;
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- break;
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- }
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- }
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-
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- return (valid) ? MODE_OK : MODE_BAD;
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-}
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-
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static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder)
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{
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}
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@@ -433,7 +413,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -450,7 +429,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -470,7 +448,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -488,7 +465,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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@@ -501,7 +477,6 @@ static struct rockchip_hdmi_chip_data rk
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};
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static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
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- .mode_valid = dw_hdmi_rockchip_mode_valid,
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.mpll_cfg = rockchip_mpll_cfg,
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.cur_ctr = rockchip_cur_ctr,
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.phy_config = rockchip_phy_config,
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