mirror of
https://github.com/coolsnowwolf/lede.git
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107 lines
2.8 KiB
Diff
107 lines
2.8 KiB
Diff
From 414fe5e5ddd91f3977617464c09a6af04e3d38ae Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Fri, 8 Apr 2022 13:22:23 +0200
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Subject: [PATCH 34/50] drm/rockchip: dw_hdmi: add regulator support
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The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
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for the HDMI port. add support for these to the driver for boards which
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have them supplied by switchable regulators.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++--
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1 file changed, 38 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -9,6 +9,7 @@
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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+#include <linux/regulator/consumer.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_edid.h>
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@@ -76,6 +77,8 @@ struct rockchip_hdmi {
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struct clk *ref_clk;
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struct clk *grf_clk;
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struct dw_hdmi *hdmi;
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+ struct regulator *avdd_0v9;
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+ struct regulator *avdd_1v8;
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struct phy *phy;
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};
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@@ -226,6 +229,14 @@ static int rockchip_hdmi_parse_dt(struct
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return PTR_ERR(hdmi->grf_clk);
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}
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+ hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
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+ if (IS_ERR(hdmi->avdd_0v9))
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+ return PTR_ERR(hdmi->avdd_0v9);
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+
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+ hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
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+ if (IS_ERR(hdmi->avdd_1v8))
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+ return PTR_ERR(hdmi->avdd_1v8);
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+
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return 0;
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}
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@@ -566,11 +577,23 @@ static int dw_hdmi_rockchip_bind(struct
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return ret;
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}
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+ ret = regulator_enable(hdmi->avdd_0v9);
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+ if (ret) {
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+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
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+ goto err_avdd_0v9;
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+ }
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+
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+ ret = regulator_enable(hdmi->avdd_1v8);
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+ if (ret) {
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+ DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
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+ goto err_avdd_1v8;
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+ }
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+
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ret = clk_prepare_enable(hdmi->ref_clk);
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if (ret) {
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DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
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ret);
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- return ret;
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+ goto err_clk;
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}
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if (hdmi->chip_data == &rk3568_chip_data) {
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@@ -594,10 +617,19 @@ static int dw_hdmi_rockchip_bind(struct
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*/
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if (IS_ERR(hdmi->hdmi)) {
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ret = PTR_ERR(hdmi->hdmi);
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- drm_encoder_cleanup(encoder);
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- clk_disable_unprepare(hdmi->ref_clk);
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+ goto err_bind;
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}
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+ return 0;
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+
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+err_bind:
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+ clk_disable_unprepare(hdmi->ref_clk);
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+ drm_encoder_cleanup(encoder);
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+err_clk:
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+ regulator_disable(hdmi->avdd_1v8);
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+err_avdd_1v8:
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+ regulator_disable(hdmi->avdd_0v9);
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+err_avdd_0v9:
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return ret;
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}
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@@ -608,6 +640,9 @@ static void dw_hdmi_rockchip_unbind(stru
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dw_hdmi_unbind(hdmi->hdmi);
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clk_disable_unprepare(hdmi->ref_clk);
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+
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+ regulator_disable(hdmi->avdd_1v8);
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+ regulator_disable(hdmi->avdd_0v9);
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}
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static const struct component_ops dw_hdmi_rockchip_ops = {
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