mirror of
https://github.com/coolsnowwolf/lede.git
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92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
From ac6f3d88fd9f6fd241bf6cfacb850f6c644a97d7 Mon Sep 17 00:00:00 2001
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From: Sascha Hauer <s.hauer@pengutronix.de>
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Date: Fri, 8 Apr 2022 13:22:18 +0200
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Subject: [PATCH 29/50] drm/rockchip: dw_hdmi: rename vpll clock to reference
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clock
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"vpll" is a misnomer. A clock input to a device should be named after
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the usage in the device, not after the clock that drives it. On the
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rk3568 the same clock is driven by the HPLL.
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To fix that, this patch renames the vpll clock to ref clock. The clock
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name "vpll" is left for compatibility to old device trees.
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Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
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---
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drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++----------
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1 file changed, 14 insertions(+), 13 deletions(-)
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--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
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@@ -69,7 +69,7 @@ struct rockchip_hdmi {
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struct regmap *regmap;
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struct rockchip_encoder encoder;
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const struct rockchip_hdmi_chip_data *chip_data;
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- struct clk *vpll_clk;
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+ struct clk *ref_clk;
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struct clk *grf_clk;
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struct dw_hdmi *hdmi;
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struct phy *phy;
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@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct
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return PTR_ERR(hdmi->regmap);
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}
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- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
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- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
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- hdmi->vpll_clk = NULL;
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- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
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+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
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+ if (!hdmi->ref_clk)
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+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
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+
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+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
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return -EPROBE_DEFER;
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- } else if (IS_ERR(hdmi->vpll_clk)) {
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- DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n");
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- return PTR_ERR(hdmi->vpll_clk);
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+ } else if (IS_ERR(hdmi->ref_clk)) {
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+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
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+ return PTR_ERR(hdmi->ref_clk);
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}
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hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
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@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mod
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{
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struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
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- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
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+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
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}
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static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
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@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct
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return ret;
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}
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- ret = clk_prepare_enable(hdmi->vpll_clk);
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+ ret = clk_prepare_enable(hdmi->ref_clk);
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if (ret) {
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- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
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+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
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ret);
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return ret;
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}
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@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct
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if (IS_ERR(hdmi->hdmi)) {
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ret = PTR_ERR(hdmi->hdmi);
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drm_encoder_cleanup(encoder);
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- clk_disable_unprepare(hdmi->vpll_clk);
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+ clk_disable_unprepare(hdmi->ref_clk);
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}
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return ret;
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@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(stru
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struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
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dw_hdmi_unbind(hdmi->hdmi);
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- clk_disable_unprepare(hdmi->vpll_clk);
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+ clk_disable_unprepare(hdmi->ref_clk);
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}
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static const struct component_ops dw_hdmi_rockchip_ops = {
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