mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
42 lines
1.1 KiB
Diff
42 lines
1.1 KiB
Diff
From 9981e62d40223e6ec7887db0c283ab404c9e9619 Mon Sep 17 00:00:00 2001
|
|
From: Peter Geis <pgwipeout@gmail.com>
|
|
Date: Wed, 11 May 2022 11:01:17 -0400
|
|
Subject: [PATCH 24/50] arm64: dts: rockchip: enable sfc controller on Quartz64
|
|
Model A
|
|
|
|
Add the sfc controller binding for the Quartz64 Model A. This is not
|
|
populated by default, so leave it disabled.
|
|
|
|
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
|
Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
---
|
|
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++
|
|
1 file changed, 16 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
|
|
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
|
|
@@ -651,6 +651,22 @@
|
|
status = "okay";
|
|
};
|
|
|
|
+&sfc {
|
|
+ pinctrl-0 = <&fspi_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <24000000>;
|
|
+ spi-rx-bus-width = <4>;
|
|
+ spi-tx-bus-width = <1>;
|
|
+ };
|
|
+};
|
|
+
|
|
/* spdif is exposed on con40 pin 18 */
|
|
&spdif {
|
|
status = "okay";
|