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54bb95de0f
lede/target/linux/sunxi/patches-6.6/501-h616-Add-cpu-frequency-scaling-support.patch
aiamadeus 54bb95de0f target: add some missing patches
2024-04-30 20:19:35 +08:00

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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: AGM1968 <AGM1968@users.noreply.github.com>
Date: Tue, 23 May 2023 16:43:00 +0000
Subject: arm64-dts-allwinner-h616-Add-efuse_xlate-cpu-frequency-scaling
Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
---
arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi | 75 ++++++++
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 91 +++++++---
3 files changed, 143 insertions(+), 24 deletions(-)
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp.dtsi
@@ -0,0 +1,75 @@
+//SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//Testing Version 1 from: AGM1968 <AGM1968@users.noreply.github.com>
+//Noted: PLL_CPUX = 24 MHz*N/P (WIP)
+
+/ {
+ cpu_opp_table: opp-table-cpu {
+ compatible = "allwinner,sun50i-h616-operating-points";
+ nvmem-cells = <&cpu_speed_grade>;
+ opp-shared;
+
+ opp-480000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt-speed0 = <820000 820000 1100000>;
+ opp-microvolt-speed1 = <880000 880000 1100000>;
+ opp-microvolt-speed2 = <880000 880000 1100000>;
+ };
+
+ opp-600000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0 = <820000 820000 1100000>;
+ opp-microvolt-speed1 = <880000 880000 1100000>;
+ opp-microvolt-speed2 = <880000 880000 1100000>;
+ };
+
+ opp-792000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <792000000>;
+ opp-microvolt-speed0 = <860000 860000 1100000>;
+ opp-microvolt-speed1 = <940000 940000 1100000>;
+ opp-microvolt-speed2 = <940000 940000 1100000>;
+ };
+
+ opp-1008000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt-speed0 = <900000 900000 1100000>;
+ opp-microvolt-speed1 = <1020000 1020000 1100000>;
+ opp-microvolt-speed2 = <1020000 1020000 1100000>;
+ };
+
+ opp-1200000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0 = <960000 960000 1100000>;
+ opp-microvolt-speed1 = <1100000 1100000 1100000>;
+ opp-microvolt-speed2 = <1100000 1100000 1100000>;
+ };
+
+ opp-1512000000 {
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt-speed0 = <1100000 1100000 1100000>;
+ opp-microvolt-speed1 = <1100000 1100000 1100000>;
+ opp-microvolt-speed2 = <1100000 1100000 1100000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu1 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu2 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
+
+&cpu3 {
+ operating-points-v2 = <&cpu_opp_table>;
+};
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -104,6 +104,8 @@ static const struct of_device_id allowli
*/
static const struct of_device_id blocklist[] __initconst = {
{ .compatible = "allwinner,sun50i-h6", },
+ { .compatible = "allwinner,sun50i-h616", },
+ { .compatible = "allwinner,sun50i-h618", },
{ .compatible = "apple,arm-platform", },
--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
@@ -6,6 +6,9 @@
* provide the OPP framework with required information.
*
* Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
+ *
+ * ADD efuse_xlate to extract SoC version so that h6 and h616 can coexist.
+ * Version 1 AGM1968 <AGM1968@users.noreply.github.com>
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
@@ -20,25 +23,62 @@
#define MAX_NAME_LEN 7
-#define NVMEM_MASK 0x7
-#define NVMEM_SHIFT 5
+#define SUN50I_H616_NVMEM_MASK 0x22
+#define SUN50I_H616_NVMEM_SHIFT 5
+#define SUN50I_H6_NVMEM_MASK 0x7
+#define SUN50I_H6_NVMEM_SHIFT 5
+
+struct sunxi_cpufreq_soc_data {
+ u32 (*efuse_xlate) (void *efuse);
+};
static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
+static u32 sun50i_h616_efuse_xlate(void *efuse)
+{
+ u32 efuse_value = (*(u32 *)efuse >> SUN50I_H616_NVMEM_SHIFT) &
+ SUN50I_H616_NVMEM_MASK;
+
+ /* Tested as V1 h616 soc. Expected efuse values are 1 - 3,
+ slowest to fastest */
+ if (efuse_value >=1 && efuse_value <= 3)
+ return efuse_value - 1;
+ else
+ return 0;
+};
+
+static u32 sun50i_h6_efuse_xlate(void *efuse)
+{
+ u32 efuse_value = (*(u32 *)efuse >> SUN50I_H6_NVMEM_SHIFT) &
+ SUN50I_H6_NVMEM_MASK;
+
+ /*
+ * We treat unexpected efuse values as if the SoC was from
+ * the slowest bin. Expected efuse values are 1 - 3, slowest
+ * to fastest.
+ */
+ if (efuse_value >= 1 && efuse_value <= 3)
+ return efuse_value - 1;
+ else
+ return 0;
+};
+
+
/**
* sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
+ * @soc_data: pointer to sunxi_cpufreq_soc_data context
* @versions: Set to the value parsed from efuse
*
* Returns 0 if success.
*/
-static int sun50i_cpufreq_get_efuse(u32 *versions)
+static int sun50i_cpufreq_get_efuse(const struct sunxi_cpufreq_soc_data *soc_data,
+ u32 *versions)
{
struct nvmem_cell *speedbin_nvmem;
struct device_node *np;
struct device *cpu_dev;
- u32 *speedbin, efuse_value;
+ u32 *speedbin;
size_t len;
- int ret;
cpu_dev = get_cpu_device(0);
if (!cpu_dev)
@@ -47,10 +87,9 @@ static int sun50i_cpufreq_get_efuse(u32
np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
if (!np)
return -ENOENT;
-
- ret = of_device_is_compatible(np,
- "allwinner,sun50i-h6-operating-points");
- if (!ret) {
+ if (of_device_is_compatible(np, "allwinner,sun50i-h6-operating-points")) {}
+ else if (of_device_is_compatible(np, "allwinner,sun50i-h616-operating-points")) {}
+ else {
of_node_put(np);
return -ENOENT;
}
@@ -66,17 +105,7 @@ static int sun50i_cpufreq_get_efuse(u32
if (IS_ERR(speedbin))
return PTR_ERR(speedbin);
- efuse_value = (*speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
-
- /*
- * We treat unexpected efuse values as if the SoC was from
- * the slowest bin. Expected efuse values are 1-3, slowest
- * to fastest.
- */
- if (efuse_value >= 1 && efuse_value <= 3)
- *versions = efuse_value - 1;
- else
- *versions = 0;
+ *versions = soc_data->efuse_xlate(speedbin);
kfree(speedbin);
return 0;
@@ -84,18 +113,23 @@ static int sun50i_cpufreq_get_efuse(u32
static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
{
+ const struct of_device_id *match;
int *opp_tokens;
char name[MAX_NAME_LEN];
unsigned int cpu;
u32 speed = 0;
int ret;
+ match = dev_get_platdata(&pdev->dev);
+ if (!match)
+ return -EINVAL;
+
opp_tokens = kcalloc(num_possible_cpus(), sizeof(*opp_tokens),
GFP_KERNEL);
if (!opp_tokens)
return -ENOMEM;
- ret = sun50i_cpufreq_get_efuse(&speed);
+ ret = sun50i_cpufreq_get_efuse(match-> data, &speed);
if (ret) {
kfree(opp_tokens);
return ret;
@@ -158,8 +192,18 @@ static struct platform_driver sun50i_cpu
},
};
+static const struct sunxi_cpufreq_soc_data sun50i_h616_data = {
+ .efuse_xlate = sun50i_h616_efuse_xlate,
+};
+
+static const struct sunxi_cpufreq_soc_data sun50i_h6_data = {
+ .efuse_xlate = sun50i_h6_efuse_xlate,
+};
+
static const struct of_device_id sun50i_cpufreq_match_list[] = {
- { .compatible = "allwinner,sun50i-h6" },
+ { .compatible = "allwinner,sun50i-h6", .data = &sun50i_h6_data },
+ { .compatible = "allwinner,sun50i-h616", .data = &sun50i_h616_data },
+ { .compatible = "allwinner,sun50i-h618", .data = &sun50i_h616_data },
{}
};
MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
@@ -195,8 +239,8 @@ static int __init sun50i_cpufreq_init(vo
return ret;
sun50i_cpufreq_pdev =
- platform_device_register_simple("sun50i-cpufreq-nvmem",
- -1, NULL, 0);
+ platform_device_register_data(NULL,
+ "sun50i-cpufreq-nvmem", -1, match, sizeof(*match));
ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
if (ret == 0)
return 0;
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