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52a7bf68d5
Allow selecting 6.6 as testing kernel on sunxi. Runtime-tested: - Linksprite pcDuino (cortexa8) - Olimex A20 Micro (cortexa7) - Pine64 SoM (cortexa53) Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
80 lines
3.2 KiB
Diff
80 lines
3.2 KiB
Diff
From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 19 Feb 2024 15:36:35 +0000
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Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
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So far we were ORing in some "unknown" value into the THS control
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register on the Allwinner H6. This part of the register is not explained
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in the H6 manual, but the H616 manual details those bits, and on closer
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inspection the THS IP blocks in both SoCs seem very close:
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- The BSP code for both SoCs writes the same values into THS_CTRL.
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- The reset values of at least the first three registers are the same.
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Replace the "unknown" value with its proper meaning: "acquire time",
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most probably the sample part of the sample & hold circuit of the ADC,
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according to its explanation in the H616 manual.
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No functional change, just a macro rename and adjustment.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
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---
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drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
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1 file changed, 16 insertions(+), 13 deletions(-)
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--- a/drivers/thermal/sun8i_thermal.c
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+++ b/drivers/thermal/sun8i_thermal.c
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@@ -50,7 +50,8 @@
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#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
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#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
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-#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
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+#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
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+#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
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#define SUN50I_THS_FILTER_EN BIT(2)
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#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
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#define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
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@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
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return 0;
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}
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-/*
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- * Without this undocumented value, the returned temperatures would
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- * be higher than real ones by about 20C.
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- */
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-#define SUN50I_H6_CTRL0_UNK 0x0000002f
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-
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static int sun50i_h6_thermal_init(struct ths_device *tmdev)
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{
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int val;
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/*
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- * T_acq = 20us
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- * clkin = 24MHz
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- *
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- * x = T_acq * clkin - 1
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- * = 479
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+ * The manual recommends an overall sample frequency of 50 KHz (20us,
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+ * 480 cycles at 24 MHz), which provides plenty of time for both the
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+ * acquisition time (>24 cycles) and the actual conversion time
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+ * (>14 cycles).
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+ * The lower half of the CTRL register holds the "acquire time", in
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+ * clock cycles, which the manual recommends to be 2us:
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+ * 24MHz * 2us = 48 cycles.
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+ * The high half of THS_CTRL encodes the sample frequency, in clock
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+ * cycles: 24MHz * 20us = 480 cycles.
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+ * This is explained in the H616 manual, but apparently wrongly
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+ * described in the H6 manual, although the BSP code does the same
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+ * for both SoCs.
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*/
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regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
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- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
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+ SUN50I_THS_CTRL0_T_ACQ(48) |
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+ SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
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/* average over 4 samples */
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regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
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SUN50I_THS_FILTER_EN |
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