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139 lines
3.7 KiB
Diff
139 lines
3.7 KiB
Diff
Document Rockchip UFS host controller for RK3576 SoC.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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---
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Changes in v5:
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- use ufshc for devicetree example suggested by Mani
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Changes in v4:
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- properly describe reset-gpios
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Changes in v3:
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- rename the file to rockchip,rk3576-ufshc.yaml
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- add description for reset-gpios
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- use rockchip,rk3576-ufshc as compatible
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Changes in v2:
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- rename the file
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- add reset-gpios
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.../bindings/ufs/rockchip,rk3576-ufshc.yaml | 105 +++++++++++++++++++++
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1 file changed, 105 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml
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diff --git a/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml
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new file mode 100644
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index 0000000..7d6c038
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/ufs/rockchip,rk3576-ufshc.yaml
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@@ -0,0 +1,105 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Rockchip UFS Host Controller
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+
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+maintainers:
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+ - Shawn Lin <shawn.lin@rock-chips.com>
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+
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+allOf:
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+ - $ref: ufs-common.yaml
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+
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+properties:
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+ compatible:
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+ const: rockchip,rk3576-ufshc
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+
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+ reg:
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+ maxItems: 5
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+
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+ reg-names:
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+ items:
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+ - const: hci
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+ - const: mphy
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+ - const: hci_grf
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+ - const: mphy_grf
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+ - const: hci_apb
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+
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+ clocks:
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+ maxItems: 4
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+
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+ clock-names:
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+ items:
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+ - const: core
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+ - const: pclk
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+ - const: pclk_mphy
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+ - const: ref_out
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+
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+ power-domains:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 4
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+
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+ reset-names:
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+ items:
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+ - const: biu
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+ - const: sys
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+ - const: ufs
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+ - const: grf
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+
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+ reset-gpios:
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+ maxItems: 1
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+ description: |
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+ GPIO specifiers for host to reset the whole UFS device including PHY and
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+ memory. This gpio is active low and should choose the one whose high output
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+ voltage is lower than 1.5V based on the UFS spec.
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+
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+required:
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+ - compatible
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+ - reg
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+ - reg-names
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+ - clocks
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+ - clock-names
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+ - interrupts
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+ - power-domains
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+ - resets
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+ - reset-names
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+ - reset-gpios
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/rockchip,rk3576-cru.h>
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+ #include <dt-bindings/reset/rockchip,rk3576-cru.h>
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+ #include <dt-bindings/interrupt-controller/arm-gic.h>
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+ #include <dt-bindings/power/rockchip,rk3576-power.h>
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+ #include <dt-bindings/pinctrl/rockchip.h>
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+ #include <dt-bindings/gpio/gpio.h>
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+
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ ufshc: ufshc@2a2d0000 {
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+ compatible = "rockchip,rk3576-ufshc";
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+ reg = <0x0 0x2a2d0000 0x0 0x10000>,
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+ <0x0 0x2b040000 0x0 0x10000>,
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+ <0x0 0x2601f000 0x0 0x1000>,
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+ <0x0 0x2603c000 0x0 0x1000>,
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+ <0x0 0x2a2e0000 0x0 0x10000>;
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+ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
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+ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
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+ <&cru CLK_REF_UFS_CLKOUT>;
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+ clock-names = "core", "pclk", "pclk_mphy", "ref_out";
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+ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_USB>;
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+ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>,
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+ <&cru SRST_P_UFS_GRF>;
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+ reset-names = "biu", "sys", "ufs", "grf";
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+ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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--
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2.7.4
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