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4d84789cdd
Manually rebased: hack-5.15/780-usb-net-MeigLink_modem_support.patch Removed upstreamed: mpc85xx/patches-5.15/110-gpio-mpc8xxx-Fix-support-for-IRQ_TYPE_LEVEL_LOW-flow.patch All other patches automatically rebased. Signed-off-by: Liu Linhui <liulinhui36@gmail.com> Signed-off-by: Liu Linhui <liulinhui36@gmail.com>
217 lines
5.9 KiB
Diff
217 lines
5.9 KiB
Diff
From 184c9b73285f05ebc013205d54ed11cd968cb38e Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 20 Dec 2021 15:08:04 +0100
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Subject: [PATCH 112/137] arm64: dts: ipq8074: fix PCI related DT nodes
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Currently present PCI PHY and PCI controller nodes are not working
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and are incorrect for the v2 of IPQ8074 which is the only version
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supported upstream.
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So, correct the PCI related nodes.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 93 +++++++++++++++------------
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1 file changed, 52 insertions(+), 41 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -232,59 +232,61 @@
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status = "disabled";
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};
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- pcie_qmp0: phy@86000 {
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- compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x00086000 0x1000>;
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+ pcie_qmp0: phy@84000 {
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+ compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
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+ reg = <0x00084000 0x1bc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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- <&gcc GCC_PCIE0_AHB_CLK>;
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+ <&gcc GCC_PCIE0_AHB_CLK>;
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clock-names = "aux", "cfg_ahb";
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+
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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- <&gcc GCC_PCIE0PHY_PHY_BCR>;
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- reset-names = "phy",
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- "common";
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+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
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+ reset-names = "phy", "common";
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+
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status = "disabled";
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- pcie_phy0: phy@86200 {
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- reg = <0x86200 0x16c>,
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- <0x86400 0x200>,
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- <0x86800 0x4f4>;
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+ pcie_phy0: phy@84200 {
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+ reg = <0x84200 0x16c>,
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+ <0x84400 0x200>,
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+ <0x84800 0x4f4>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "pcie_0_pipe_clk";
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+ clock-output-names = "gcc_pcie0_pipe_clk_src";
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};
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};
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pcie_qmp1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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- reg = <0x0008e000 0x1000>;
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+ reg = <0x0008e000 0x1c4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE1_AUX_CLK>,
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- <&gcc GCC_PCIE1_AHB_CLK>;
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+ <&gcc GCC_PCIE1_AHB_CLK>;
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clock-names = "aux", "cfg_ahb";
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+
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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- <&gcc GCC_PCIE1PHY_PHY_BCR>;
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- reset-names = "phy",
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- "common";
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+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
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+ reset-names = "phy", "common";
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+
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status = "disabled";
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pcie_phy1: phy@8e200 {
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- reg = <0x8e200 0x16c>,
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+ reg = <0x8e200 0x130>,
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<0x8e400 0x200>,
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- <0x8e800 0x4f4>;
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+ <0x8e800 0x1f8>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "pcie_1_pipe_clk";
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+ clock-output-names = "gcc_pcie1_pipe_clk_src";
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};
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};
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@@ -686,7 +688,7 @@
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
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ranges = <0 0xb00a000 0xffd>;
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- v2m@0 {
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+ gic_v2m0: v2m@0 {
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compatible = "arm,gic-v2m-frame";
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msi-controller;
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reg = <0x0 0xffd>;
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@@ -787,6 +789,7 @@
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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+ max-link-speed = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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@@ -794,12 +797,12 @@
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x10200000 0x10200000
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- 0 0x100000 /* downstream I/O */
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- 0x82000000 0 0x10300000 0x10300000
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- 0 0xd00000>; /* non-prefetchable memory */
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+ 0 0x10000>, /* downstream I/O */
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+ <0x82000000 0 0x10220000 0x10220000
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+ 0 0xfde0000>; /* non-prefetchable memory */
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+
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+ msi-parent = <&gic_v2m0>;
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142
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@@ -839,16 +842,18 @@
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};
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pcie0: pci@20000000 {
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- compatible = "qcom,pcie-ipq8074";
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- reg = <0x20000000 0xf1d>,
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- <0x20000f20 0xa8>,
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- <0x00080000 0x2000>,
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- <0x20100000 0x1000>;
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- reg-names = "dbi", "elbi", "parf", "config";
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+ compatible = "qcom,pcie-ipq8074-gen3";
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+ reg = <0x20000000 0xf1d>,
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+ <0x20000f20 0xa8>,
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+ <0x20001000 0x1000>,
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+ <0x00080000 0x4000>,
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+ <0x20100000 0x1000>;
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+ reg-names = "dbi", "elbi", "atu", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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+ max-link-speed = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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@@ -856,12 +861,12 @@
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x20200000 0x20200000
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- 0 0x100000 /* downstream I/O */
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- 0x82000000 0 0x20300000 0x20300000
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- 0 0xd00000>; /* non-prefetchable memory */
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+ 0 0x10000>, /* downstream I/O */
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+ <0x82000000 0 0x20220000 0x20220000
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+ 0 0xfde0000>; /* non-prefetchable memory */
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+
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+ msi-parent = <&gic_v2m0>;
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- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 75
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@@ -877,27 +882,33 @@
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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<&gcc GCC_PCIE0_AXI_S_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>,
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- <&gcc GCC_PCIE0_AUX_CLK>;
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+ <&gcc GCC_PCIE0_AUX_CLK>,
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+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
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+ <&gcc GCC_PCIE0_RCHNG_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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- "aux";
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+ "aux",
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+ "axi_bridge",
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+ "rchng";
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resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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<&gcc GCC_PCIE0_SLEEP_ARES>,
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<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE0_AHB_ARES>,
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- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
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+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
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+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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- "axi_m_sticky";
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+ "axi_m_sticky",
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+ "axi_s_sticky";
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status = "disabled";
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};
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};
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