mirror of
https://github.com/coolsnowwolf/lede.git
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93 lines
3.0 KiB
Diff
93 lines
3.0 KiB
Diff
From 91802f44a959582842bdbbd0190e68337ad4c60c Mon Sep 17 00:00:00 2001
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From: Kever Yang <kever.yang@rock-chips.com>
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Date: Mon, 11 Jul 2022 20:35:52 +0800
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Subject: [PATCH] phy: rockchip-snps-pcie3: rk3568: update fw when init
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This fw fix some RX issue:
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1. connect detect error;
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2. transfer error in ssd huge data write(more than 10GB).
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Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Change-Id: I6624b6af2ede3c2fca61c0f753a08a33ce69a6d2
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---
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drivers/phy/phy-rockchip-snps-pcie3.c | 36 +-
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drivers/phy/phy-rockchip-snps-pcie3.fw | 8192 ++++++++++++++++++++++++
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2 files changed, 8225 insertions(+), 3 deletions(-)
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create mode 100644 drivers/phy/phy-rockchip-snps-pcie3.fw
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -21,6 +21,7 @@
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/* Register for RK3568 */
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#define GRF_PCIE30PHY_CON1 0x4
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+#define GRF_PCIE30PHY_CON4 0x10
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
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@@ -73,6 +74,10 @@ struct rockchip_p3phy_ops {
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int (*phy_init)(struct rockchip_p3phy_priv *priv);
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};
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+static u16 phy_fw[] = {
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+ #include "p3phy.fw"
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+};
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+
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static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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@@ -97,13 +102,14 @@ static int rockchip_p3phy_rk3568_init(st
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{
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struct phy *phy = priv->phy;
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bool bifurcation = false;
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+ int i;
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int ret;
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u32 reg;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
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- for (int i = 0; i < priv->num_lanes; i++) {
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+ for (i = 0; i < priv->num_lanes; i++) {
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dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
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if (priv->lanes[i] > 1)
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bifurcation = true;
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@@ -122,16 +128,35 @@ static int rockchip_p3phy_rk3568_init(st
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GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
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}
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
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+
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reset_control_deassert(priv->p30phy);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_STATUS0,
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reg, SRAM_INIT_DONE(reg),
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0, 500);
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- if (ret)
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+ if (ret) {
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dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
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__func__, reg);
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- return ret;
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+ return ret;
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+ }
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+
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
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+ for (i = 0; i < 8192; i++)
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+ writel(phy_fw[i], priv->mmio + (i<<2));
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+
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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+ (0x0 << 8) | (0x3 << (8 + 16)));
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
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+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
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+
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+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
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+ return 0;
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}
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static const struct rockchip_p3phy_ops rk3568_ops = {
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