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https://github.com/coolsnowwolf/lede.git
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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
66 lines
2.8 KiB
Diff
66 lines
2.8 KiB
Diff
From bf8a71dbd221bf7245177f1848bbc9e10f2dfb7e Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 31 Mar 2025 14:41:45 +0100
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Subject: [PATCH] PCI: pcie-brcmstb: add more safeguards for clkreq "safe" mode
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The existing implementation for clkreq-mode="safe" leaves the HARD_DEBUG
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with both control bits clear. This can cause link failure if L1
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sub-states are enabled and if either of these conditions occurrs:
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- The platform does not connect the CLRKEQ# signal to the EP, and a
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pull-up is present on the line
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- The platform connects the signal to the EP, and the EP enters an L1.x
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or ClkPM state
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Additional register bits in the HARD_DEBUG register can be used to force
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the RC to drive CLKREQ# low. Also, un-advertise L1ss as a) additional
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power savings can't be realised and b) enabling L1ss may incur
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additional wake latency from L1.0.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 15 ++++++++++++++-
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1 file changed, 14 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -135,11 +135,15 @@
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_ENABLE_MASK 0x10000
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_OUT_MASK 0x100000
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
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#define PCIE_CLKREQ_MASK \
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(PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \
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+ PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_ENABLE_MASK | \
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+ PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_OUT_MASK | \
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PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK)
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#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
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@@ -1470,12 +1474,21 @@ static void brcm_config_clkreq(struct br
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} else {
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/*
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- * "safe" -- No power savings; refclk is driven by RC
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+ * "safe" -- No power savings; refclk and CLKREQ# are driven by RC
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* unconditionally.
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*/
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if (strcmp(mode, "safe") != 0)
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dev_err(pcie->dev, err_msg);
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mode = "safe";
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+ clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_OUT_MASK;
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+ clkreq_cntl |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_REFCLK_OVRD_ENABLE_MASK;
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+ /*
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+ * Un-advertise L1ss as configuring an EP to enter L1.x with CLKREQ#
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+ * physically unconnected will result in a dead link.
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+ */
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+ tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
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+ u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK);
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+ writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
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}
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writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie));
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