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https://github.com/coolsnowwolf/lede.git
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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
73 lines
2.5 KiB
Diff
73 lines
2.5 KiB
Diff
From 57bcfa6da45cec1329d72a95f3620255036b596d Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 17 Mar 2025 15:51:03 +0000
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Subject: [PATCH] DT: bcm2711/bcm2712: use upstream property for controlling
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pcie clkreq
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L1 sub-state support and clkreq control are intermingled in the hardware,
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and upstream now have a tri-state property to control this. The default
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behaviour is now to enable clkreq control if the property is absent.
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Default Pi 5 PCIex1 to "safe" to avoid breaking expansion boards without
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the CLKREQ# line connected. Make this explicit in the pciex1-compat-pi5
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overlay, and remove the obsolete CM4 property.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts | 4 ----
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arch/arm/boot/dts/overlays/README | 4 +++-
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arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts | 2 +-
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arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 4 ++++
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4 files changed, 8 insertions(+), 6 deletions(-)
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--- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts
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+++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts
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@@ -422,10 +422,6 @@
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// =============================================
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// Board specific stuff here
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-&pcie0 {
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- brcm,enable-l1ss;
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-};
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-
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&sdhost {
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status = "disabled";
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};
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -3703,7 +3703,9 @@ Params: <None>
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Name: pciex1-compat-pi5
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Info: Compatibility features for pciex1 on Pi 5.
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Load: dtoverlay=pciex1-compat-pi5,<param>=<val>
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-Params: l1ss Enable ASPM L1 sub-state support
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+Params: l1ss Enable RC ASPM L1 sub-state support. Requires
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+ that the CLKREQ# pin is connected to the
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+ endpoint.
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no-l0s Disable ASPM L0s
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no-mip Revert to the MSI target in the RC, instead of
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the MSI-MIP peripheral. Use if a) more than 8
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--- a/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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+++ b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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@@ -12,7 +12,7 @@
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fragment@0 {
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target = <&pciex1>;
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__dormant__ {
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- brcm,enable-l1ss;
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+ brcm,clkreq-mode = "default";
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};
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};
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--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
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@@ -713,6 +713,10 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
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clock-names = "hdmi", "bvb", "audio", "cec";
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};
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+&pcie1 {
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+ brcm,clkreq-mode = "safe";
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+};
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+
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&pcie2 {
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status = "okay";
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};
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