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https://github.com/coolsnowwolf/lede.git
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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
106 lines
3.4 KiB
Diff
106 lines
3.4 KiB
Diff
From 6ef00f8b825a5fb5dc2942e467ed251b84dea4eb Mon Sep 17 00:00:00 2001
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From: Stanimir Varbanov <svarbanov@suse.de>
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Date: Mon, 20 Jan 2025 15:01:15 +0200
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Subject: [PATCH] PCI: brcmstb: Adjust PHY PLL setup to use a 54MHz input
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refclk
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The default input reference clock for the PHY PLL is 100Mhz, except for
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some devices where it is 54Mhz like bcm2712C1 and bcm2712D0.
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To implement this adjustments introduce a new .post_setup op in
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pcie_cfg_data and call it at the end of brcm_pcie_setup function.
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The bcm2712 .post_setup callback implements the required MDIO writes that
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switch the PLL refclk and also change PHY PM clock period.
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Without this RPi5 PCIex1 is unable to enumerate endpoint devices on
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the expansion connector.
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Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 44 +++++++++++++++++++++++++++
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1 file changed, 44 insertions(+)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -55,6 +55,10 @@
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#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
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#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
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+#define PCIE_RC_PL_PHY_CTL_15 0x184c
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+#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000
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+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
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+
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#define PCIE_MISC_MISC_CTRL 0x4008
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#define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
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#define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
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@@ -251,6 +255,7 @@ struct pcie_cfg_data {
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u8 num_inbound_wins;
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int (*perst_set)(struct brcm_pcie *pcie, u32 val);
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int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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+ int (*post_setup)(struct brcm_pcie *pcie);
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};
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struct subdev_regulators {
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@@ -826,6 +831,38 @@ static int brcm_pcie_perst_set_generic(s
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return 0;
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}
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+static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie)
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+{
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+ const u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };
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+ const u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };
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+ int ret, i;
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+ u32 tmp;
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+
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+ /* Allow a 54MHz (xosc) refclk source */
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+ ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600);
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+ if (ret < 0)
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+ return ret;
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+
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+ for (i = 0; i < ARRAY_SIZE(regs); i++) {
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+ ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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+ usleep_range(100, 200);
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+
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+ /*
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+ * Set L1SS sub-state timers to avoid lengthy state transitions,
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+ * PM clock period is 18.52ns (1/54MHz, round down).
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+ */
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+ tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15);
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+ tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
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+ tmp |= 0x12;
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+ writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15);
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+
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+ return 0;
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+}
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+
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static void add_inbound_win(struct inbound_win *b, u8 *count, u64 size,
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u64 cpu_addr, u64 pci_offset)
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{
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@@ -1189,6 +1226,12 @@ static int brcm_pcie_setup(struct brcm_p
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PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
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writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
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+ if (pcie->cfg->post_setup) {
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+ ret = pcie->cfg->post_setup(pcie);
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+ if (ret < 0)
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+ return ret;
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+ }
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+
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return 0;
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}
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@@ -1717,6 +1760,7 @@ static const struct pcie_cfg_data bcm271
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.soc_base = BCM7712,
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.perst_set = brcm_pcie_perst_set_7278,
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.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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+ .post_setup = brcm_pcie_post_setup_bcm2712,
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.quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN,
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.num_inbound_wins = 10,
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};
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