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These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
80 lines
3.0 KiB
Diff
80 lines
3.0 KiB
Diff
From c36c90dc88faa4a0ddbf7b2118ca6eba6dacc786 Mon Sep 17 00:00:00 2001
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From: Stanimir Varbanov <svarbanov@suse.de>
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Date: Fri, 25 Oct 2024 15:45:12 +0300
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Subject: [PATCH] PCI: brcmstb: Add bcm2712 support
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Add bare minimum amount of changes in order to support PCIe RC hardware
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IP found on RPi5. The PCIe controller on bcm2712 is based on bcm7712 and
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as such it inherits register offsets, perst, bridge_reset ops and inbound
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windows count.
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Although, the implementation for bcm2712 needs a workaround related to the
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control of the bridge_reset where turning off of the root port must not
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shutdown the bridge_reset and this must be avoided. To implement this
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workaround a quirks field is introduced in pcie_cfg_data struct.
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Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
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Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 25 +++++++++++++++++++++++--
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1 file changed, 23 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -234,10 +234,20 @@ struct inbound_win {
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u64 cpu_addr;
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};
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+/*
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+ * The RESCAL block is tied to PCIe controller #1, regardless of the number of
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+ * controllers, and turning off PCIe controller #1 prevents access to the RESCAL
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+ * register blocks, therefore no other controller can access this register
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+ * space, and depending upon the bus fabric we may get a timeout (UBUS/GISB),
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+ * or a hang (AXI).
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+ */
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+#define CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN BIT(0)
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+
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struct pcie_cfg_data {
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const int *offsets;
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const enum pcie_soc_base soc_base;
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const bool has_phy;
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+ const u32 quirks;
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u8 num_inbound_wins;
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int (*perst_set)(struct brcm_pcie *pcie, u32 val);
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int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
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@@ -1490,8 +1500,9 @@ static int brcm_pcie_turn_off(struct brc
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u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
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writel(tmp, base + HARD_DEBUG(pcie));
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- /* Shutdown PCIe bridge */
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- ret = pcie->bridge_sw_init_set(pcie, 1);
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+ if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN))
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+ /* Shutdown PCIe bridge */
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+ ret = pcie->cfg->bridge_sw_init_set(pcie, 1);
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return ret;
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}
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@@ -1701,6 +1712,15 @@ static const struct pcie_cfg_data bcm271
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.num_inbound_wins = 3,
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};
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+static const struct pcie_cfg_data bcm2712_cfg = {
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+ .offsets = pcie_offsets_bcm7712,
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+ .soc_base = BCM7712,
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+ .perst_set = brcm_pcie_perst_set_7278,
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+ .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
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+ .quirks = CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN,
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+ .num_inbound_wins = 10,
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+};
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+
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static const struct pcie_cfg_data bcm4908_cfg = {
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.offsets = pcie_offsets,
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.soc_base = BCM4908,
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@@ -1752,6 +1772,7 @@ static const struct pcie_cfg_data bcm771
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static const struct of_device_id brcm_pcie_match[] = {
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{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
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+ { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
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{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
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{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
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{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
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