mirror of
https://github.com/coolsnowwolf/lede.git
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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
470 lines
16 KiB
Diff
470 lines
16 KiB
Diff
From 4a142cb2a68dc279aa90f1850c4af363b29f02e7 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
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Date: Tue, 11 Mar 2025 15:13:45 -0300
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Subject: [PATCH] drm/v3d: Associate a V3D tech revision to all supported
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devices
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The V3D driver currently determines the GPU tech version (33, 41...)
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by reading a register. This approach has worked so far since this
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information wasn’t needed before powering on the GPU.
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V3D 7.1 introduces new registers that must be written to power on the
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GPU, requiring us to know the V3D version beforehand. To address this,
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associate each supported SoC with the corresponding VideoCore GPU version
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as part of the device data.
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To prevent possible mistakes, add an assertion to verify that the version
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specified in the device data matches the one reported by the hardware.
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If there is a mismatch, the kernel will trigger a warning.
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Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
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Signed-off-by: Maíra Canal <mcanal@igalia.com>
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---
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drivers/gpu/drm/v3d/v3d_debugfs.c | 126 +++++++++++++++---------------
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drivers/gpu/drm/v3d/v3d_drv.c | 60 ++++++++++++--
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drivers/gpu/drm/v3d/v3d_drv.h | 11 ++-
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drivers/gpu/drm/v3d/v3d_gem.c | 10 +--
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drivers/gpu/drm/v3d/v3d_irq.c | 6 +-
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drivers/gpu/drm/v3d/v3d_perfmon.c | 4 +-
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drivers/gpu/drm/v3d/v3d_sched.c | 6 +-
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7 files changed, 138 insertions(+), 85 deletions(-)
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--- a/drivers/gpu/drm/v3d/v3d_debugfs.c
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+++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
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@@ -21,74 +21,74 @@ struct v3d_reg_def {
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};
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static const struct v3d_reg_def v3d_hub_reg_defs[] = {
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- REGDEF(33, 42, V3D_HUB_AXICFG),
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- REGDEF(33, 71, V3D_HUB_UIFCFG),
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- REGDEF(33, 71, V3D_HUB_IDENT0),
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- REGDEF(33, 71, V3D_HUB_IDENT1),
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- REGDEF(33, 71, V3D_HUB_IDENT2),
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- REGDEF(33, 71, V3D_HUB_IDENT3),
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- REGDEF(33, 71, V3D_HUB_INT_STS),
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- REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
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-
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- REGDEF(33, 71, V3D_MMU_CTL),
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- REGDEF(33, 71, V3D_MMU_VIO_ADDR),
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- REGDEF(33, 71, V3D_MMU_VIO_ID),
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- REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
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-
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- REGDEF(71, 71, V3D_GMP_STATUS(71)),
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- REGDEF(71, 71, V3D_GMP_CFG(71)),
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- REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
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+ REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),
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+
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),
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+
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)),
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};
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static const struct v3d_reg_def v3d_gca_reg_defs[] = {
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- REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
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- REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
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+ REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
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+ REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
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};
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static const struct v3d_reg_def v3d_core_reg_defs[] = {
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- REGDEF(33, 71, V3D_CTL_IDENT0),
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- REGDEF(33, 71, V3D_CTL_IDENT1),
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- REGDEF(33, 71, V3D_CTL_IDENT2),
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- REGDEF(33, 71, V3D_CTL_MISCCFG),
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- REGDEF(33, 71, V3D_CTL_INT_STS),
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- REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
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- REGDEF(33, 71, V3D_CLE_CT0CS),
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- REGDEF(33, 71, V3D_CLE_CT0CA),
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- REGDEF(33, 71, V3D_CLE_CT0EA),
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- REGDEF(33, 71, V3D_CLE_CT1CS),
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- REGDEF(33, 71, V3D_CLE_CT1CA),
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- REGDEF(33, 71, V3D_CLE_CT1EA),
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-
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- REGDEF(33, 71, V3D_PTB_BPCA),
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- REGDEF(33, 71, V3D_PTB_BPCS),
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-
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- REGDEF(33, 42, V3D_GMP_STATUS(33)),
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- REGDEF(33, 42, V3D_GMP_CFG(33)),
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- REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
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-
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- REGDEF(33, 71, V3D_ERR_FDBGO),
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- REGDEF(33, 71, V3D_ERR_FDBGB),
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- REGDEF(33, 71, V3D_ERR_FDBGS),
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- REGDEF(33, 71, V3D_ERR_STAT),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),
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+
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),
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+
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+ REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)),
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+ REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)),
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+ REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)),
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+
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
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+ REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
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};
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static const struct v3d_reg_def v3d_csd_reg_defs[] = {
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- REGDEF(41, 71, V3D_CSD_STATUS),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
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- REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
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- REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
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- REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
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+ REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)),
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+ REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)),
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+ REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
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};
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static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
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@@ -164,7 +164,7 @@ static int v3d_v3d_debugfs_ident(struct
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str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
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seq_printf(m, "TFU: %s\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
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- if (v3d->ver <= 42) {
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+ if (v3d->ver <= V3D_GEN_42) {
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seq_printf(m, "TSY: %s\n",
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str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
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}
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@@ -196,11 +196,11 @@ static int v3d_v3d_debugfs_ident(struct
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seq_printf(m, " QPUs: %d\n", nslc * qups);
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seq_printf(m, " Semaphores: %d\n",
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V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
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- if (v3d->ver <= 42) {
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+ if (v3d->ver <= V3D_GEN_42) {
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seq_printf(m, " BCG int: %d\n",
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(ident2 & V3D_IDENT2_BCG_INT) != 0);
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}
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- if (v3d->ver < 40) {
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+ if (v3d->ver < V3D_GEN_41) {
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seq_printf(m, " Override TMU: %d\n",
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(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
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}
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@@ -234,7 +234,7 @@ static int v3d_measure_clock(struct seq_
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int core = 0;
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int measure_ms = 1000;
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- if (v3d->ver >= 40) {
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+ if (v3d->ver >= V3D_GEN_41) {
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int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
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V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
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V3D_SET_FIELD_VER(cycle_count_reg,
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--- a/drivers/gpu/drm/v3d/v3d_drv.c
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+++ b/drivers/gpu/drm/v3d/v3d_drv.c
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@@ -97,7 +97,7 @@ static int v3d_get_param_ioctl(struct dr
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args->value = 1;
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return 0;
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case DRM_V3D_PARAM_SUPPORTS_PERFMON:
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- args->value = (v3d->ver >= 40);
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+ args->value = (v3d->ver >= V3D_GEN_41);
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return 0;
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case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
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args->value = 1;
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@@ -260,15 +260,44 @@ static const struct drm_driver v3d_drm_d
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};
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static const struct of_device_id v3d_of_match[] = {
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- { .compatible = "brcm,2712-v3d" },
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- { .compatible = "brcm,2711-v3d" },
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- { .compatible = "brcm,2712-v3d" },
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- { .compatible = "brcm,7268-v3d" },
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- { .compatible = "brcm,7278-v3d" },
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+ { .compatible = "brcm,2711-v3d", .data = (void *)V3D_GEN_42 },
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+ { .compatible = "brcm,2712-v3d", .data = (void *)V3D_GEN_71 },
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+ { .compatible = "brcm,7268-v3d", .data = (void *)V3D_GEN_33 },
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+ { .compatible = "brcm,7278-v3d", .data = (void *)V3D_GEN_41 },
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{},
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};
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MODULE_DEVICE_TABLE(of, v3d_of_match);
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+static void
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+v3d_idle_sms(struct v3d_dev *v3d)
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+{
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+ if (v3d->ver < V3D_GEN_71)
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+ return;
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+
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+ V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF);
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+
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+ if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) {
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+ DRM_ERROR("Failed to power up SMS\n");
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+ }
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+
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+ v3d_reset_sms(v3d);
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+}
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+
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+static void
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+v3d_power_off_sms(struct v3d_dev *v3d)
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+{
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+ if (v3d->ver < V3D_GEN_71)
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+ return;
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+
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+ V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF);
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+
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+ if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) {
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+ DRM_ERROR("Failed to power off SMS\n");
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+ }
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+}
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+
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static int
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map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
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{
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@@ -283,6 +312,7 @@ static int v3d_platform_drm_probe(struct
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struct device_node *node;
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struct drm_device *drm;
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struct v3d_dev *v3d;
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+ enum v3d_gen gen;
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int ret;
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u32 mmu_debug;
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u32 ident1, ident3;
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@@ -296,6 +326,9 @@ static int v3d_platform_drm_probe(struct
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platform_set_drvdata(pdev, drm);
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+ gen = (enum v3d_gen)of_device_get_match_data(dev);
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+ v3d->ver = gen;
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+
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ret = map_regs(v3d, &v3d->hub_regs, "hub");
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if (ret)
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return ret;
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@@ -304,6 +337,12 @@ static int v3d_platform_drm_probe(struct
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if (ret)
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return ret;
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+ if (v3d->ver >= V3D_GEN_71) {
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+ ret = map_regs(v3d, &v3d->sms_regs, "sms");
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+ if (ret)
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+ return ret;
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+ }
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+
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v3d->clk = devm_clk_get_optional(dev, NULL);
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if (IS_ERR(v3d->clk))
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return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
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@@ -314,6 +353,8 @@ static int v3d_platform_drm_probe(struct
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return ret;
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}
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+ v3d_idle_sms(v3d);
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+
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mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
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mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
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ret = dma_set_mask_and_coherent(dev, mask);
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@@ -325,6 +366,11 @@ static int v3d_platform_drm_probe(struct
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ident1 = V3D_READ(V3D_HUB_IDENT1);
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v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
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V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
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+ /* Make sure that the V3D tech version retrieved from the HW is equal
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+ * to the one advertised by the device tree.
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+ */
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+ WARN_ON(v3d->ver != gen);
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+
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v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
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WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
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@@ -377,7 +423,7 @@ static int v3d_platform_drm_probe(struct
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v3d->clk_down_rate =
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(clk_get_rate(clk_get_parent(v3d->clk)) / (1 << 4)) + 10000;
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- if (v3d->ver < 41) {
|
||
+ if (v3d->ver < V3D_GEN_41) {
|
||
ret = map_regs(v3d, &v3d->gca_regs, "gca");
|
||
if (ret)
|
||
goto clk_disable;
|
||
--- a/drivers/gpu/drm/v3d/v3d_drv.h
|
||
+++ b/drivers/gpu/drm/v3d/v3d_drv.h
|
||
@@ -94,11 +94,18 @@ struct v3d_perfmon {
|
||
u64 values[] __counted_by(ncounters);
|
||
};
|
||
|
||
+enum v3d_gen {
|
||
+ V3D_GEN_33 = 33,
|
||
+ V3D_GEN_41 = 41,
|
||
+ V3D_GEN_42 = 42,
|
||
+ V3D_GEN_71 = 71,
|
||
+};
|
||
+
|
||
struct v3d_dev {
|
||
struct drm_device drm;
|
||
|
||
/* Short representation (e.g. 33, 41) of the V3D tech version */
|
||
- int ver;
|
||
+ enum v3d_gen ver;
|
||
|
||
/* Short representation (e.g. 5, 6) of the V3D tech revision */
|
||
int rev;
|
||
@@ -205,7 +212,7 @@ to_v3d_dev(struct drm_device *dev)
|
||
static inline bool
|
||
v3d_has_csd(struct v3d_dev *v3d)
|
||
{
|
||
- return v3d->ver >= 41;
|
||
+ return v3d->ver >= V3D_GEN_41;
|
||
}
|
||
|
||
#define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
|
||
--- a/drivers/gpu/drm/v3d/v3d_gem.c
|
||
+++ b/drivers/gpu/drm/v3d/v3d_gem.c
|
||
@@ -26,7 +26,7 @@ v3d_init_core(struct v3d_dev *v3d, int c
|
||
* type. If you want the default behavior, you can still put
|
||
* "2" in the indirect texture state's output_type field.
|
||
*/
|
||
- if (v3d->ver < 40)
|
||
+ if (v3d->ver < V3D_GEN_41)
|
||
V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT);
|
||
|
||
/* Whenever we flush the L2T cache, we always want to flush
|
||
@@ -59,7 +59,7 @@ v3d_idle_axi(struct v3d_dev *v3d, int co
|
||
static void
|
||
v3d_idle_gca(struct v3d_dev *v3d)
|
||
{
|
||
- if (v3d->ver >= 41)
|
||
+ if (v3d->ver >= V3D_GEN_41)
|
||
return;
|
||
|
||
V3D_GCA_WRITE(V3D_GCA_SAFE_SHUTDOWN, V3D_GCA_SAFE_SHUTDOWN_EN);
|
||
@@ -133,13 +133,13 @@ v3d_reset(struct v3d_dev *v3d)
|
||
static void
|
||
v3d_flush_l3(struct v3d_dev *v3d)
|
||
{
|
||
- if (v3d->ver < 41) {
|
||
+ if (v3d->ver < V3D_GEN_41) {
|
||
u32 gca_ctrl = V3D_GCA_READ(V3D_GCA_CACHE_CTRL);
|
||
|
||
V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
|
||
gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH);
|
||
|
||
- if (v3d->ver < 33) {
|
||
+ if (v3d->ver < V3D_GEN_33) {
|
||
V3D_GCA_WRITE(V3D_GCA_CACHE_CTRL,
|
||
gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH);
|
||
}
|
||
@@ -152,7 +152,7 @@ v3d_flush_l3(struct v3d_dev *v3d)
|
||
static void
|
||
v3d_invalidate_l2c(struct v3d_dev *v3d, int core)
|
||
{
|
||
- if (v3d->ver > 32)
|
||
+ if (v3d->ver >= V3D_GEN_33)
|
||
return;
|
||
|
||
V3D_CORE_WRITE(core, V3D_CTL_L2CACTL,
|
||
--- a/drivers/gpu/drm/v3d/v3d_irq.c
|
||
+++ b/drivers/gpu/drm/v3d/v3d_irq.c
|
||
@@ -143,7 +143,7 @@ v3d_irq(int irq, void *arg)
|
||
/* We shouldn't be triggering these if we have GMP in
|
||
* always-allowed mode.
|
||
*/
|
||
- if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
|
||
+ if (v3d->ver < V3D_GEN_71 && (intsts & V3D_INT_GMPV))
|
||
dev_err(v3d->drm.dev, "GMP violation\n");
|
||
|
||
/* V3D 4.2 wires the hub and core IRQs together, so if we &
|
||
@@ -201,7 +201,7 @@ v3d_hub_irq(int irq, void *arg)
|
||
|
||
V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
|
||
|
||
- if (v3d->ver >= 41) {
|
||
+ if (v3d->ver >= V3D_GEN_41) {
|
||
axi_id = axi_id >> 5;
|
||
if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
|
||
client = v3d41_axi_ids[axi_id];
|
||
@@ -220,7 +220,7 @@ v3d_hub_irq(int irq, void *arg)
|
||
status = IRQ_HANDLED;
|
||
}
|
||
|
||
- if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
|
||
+ if (v3d->ver >= V3D_GEN_71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
|
||
dev_err(v3d->drm.dev, "GMP Violation\n");
|
||
status = IRQ_HANDLED;
|
||
}
|
||
--- a/drivers/gpu/drm/v3d/v3d_perfmon.c
|
||
+++ b/drivers/gpu/drm/v3d/v3d_perfmon.c
|
||
@@ -200,10 +200,10 @@ void v3d_perfmon_init(struct v3d_dev *v3
|
||
const struct v3d_perf_counter_desc *counters = NULL;
|
||
unsigned int max = 0;
|
||
|
||
- if (v3d->ver >= 71) {
|
||
+ if (v3d->ver >= V3D_GEN_71) {
|
||
counters = v3d_v71_performance_counters;
|
||
max = ARRAY_SIZE(v3d_v71_performance_counters);
|
||
- } else if (v3d->ver >= 42) {
|
||
+ } else if (v3d->ver >= V3D_GEN_42) {
|
||
counters = v3d_v42_performance_counters;
|
||
max = ARRAY_SIZE(v3d_v42_performance_counters);
|
||
}
|
||
--- a/drivers/gpu/drm/v3d/v3d_sched.c
|
||
+++ b/drivers/gpu/drm/v3d/v3d_sched.c
|
||
@@ -357,11 +357,11 @@ v3d_tfu_job_run(struct drm_sched_job *sc
|
||
V3D_WRITE(V3D_TFU_ICA(v3d->ver), job->args.ica);
|
||
V3D_WRITE(V3D_TFU_IUA(v3d->ver), job->args.iua);
|
||
V3D_WRITE(V3D_TFU_IOA(v3d->ver), job->args.ioa);
|
||
- if (v3d->ver >= 71)
|
||
+ if (v3d->ver >= V3D_GEN_71)
|
||
V3D_WRITE(V3D_V7_TFU_IOC, job->args.v71.ioc);
|
||
V3D_WRITE(V3D_TFU_IOS(v3d->ver), job->args.ios);
|
||
V3D_WRITE(V3D_TFU_COEF0(v3d->ver), job->args.coef[0]);
|
||
- if (v3d->ver >= 71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
|
||
+ if (v3d->ver >= V3D_GEN_71 || (job->args.coef[0] & V3D_TFU_COEF0_USECOEF)) {
|
||
V3D_WRITE(V3D_TFU_COEF1(v3d->ver), job->args.coef[1]);
|
||
V3D_WRITE(V3D_TFU_COEF2(v3d->ver), job->args.coef[2]);
|
||
V3D_WRITE(V3D_TFU_COEF3(v3d->ver), job->args.coef[3]);
|
||
@@ -412,7 +412,7 @@ v3d_csd_job_run(struct drm_sched_job *sc
|
||
*
|
||
* XXX: Set the CFG7 register
|
||
*/
|
||
- if (v3d->ver >= 71)
|
||
+ if (v3d->ver >= V3D_GEN_71)
|
||
V3D_CORE_WRITE(0, V3D_V7_CSD_QUEUED_CFG7, 0);
|
||
|
||
/* CFG0 write kicks off the job. */
|