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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 8331b1fe1bbc5840b2f02387cdffedafee5fb64d Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 8 Jun 2022 17:23:47 +0100
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Subject: [PATCH] drm: vc4: dsi: Clocks should be running before reset
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The initialisation sequence differs slightly from the documentation
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in that the clocks are meant to be running before resets and
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similar.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 30 +++++++++++++++---------------
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1 file changed, 15 insertions(+), 15 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -931,6 +931,21 @@ static void vc4_dsi_bridge_pre_enable(st
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"Failed to set phy clock to %ld: %d\n", phy_clock, ret);
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}
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+ ret = clk_prepare_enable(dsi->escape_clock);
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+ if (ret) {
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+ drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
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+ ret);
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+ return;
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+ }
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+
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+ ret = clk_prepare_enable(dsi->pll_phy_clock);
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+ if (ret) {
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+ drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
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+ return;
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+ }
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+
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+ hs_clock = clk_get_rate(dsi->pll_phy_clock);
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+
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/* Reset the DSI and all its fifos. */
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DSI_PORT_WRITE(CTRL,
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DSI_CTRL_SOFT_RESET_CFG |
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@@ -989,21 +1004,6 @@ static void vc4_dsi_bridge_pre_enable(st
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mdelay(1);
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}
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- ret = clk_prepare_enable(dsi->escape_clock);
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- if (ret) {
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- drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
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- ret);
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- return;
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- }
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-
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- ret = clk_prepare_enable(dsi->pll_phy_clock);
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- if (ret) {
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- drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
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- return;
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- }
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-
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- hs_clock = clk_get_rate(dsi->pll_phy_clock);
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-
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/* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
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* not the pixel clock rate. DSIxP take from the APHY's byte,
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* DDR2, or DDR4 clock (we use byte) and feed into the PV at
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