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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
73 lines
2.9 KiB
Diff
73 lines
2.9 KiB
Diff
From cedbc264e0a53a1d99c6f5bab918cc018c2ffada Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 24 Jan 2024 16:28:19 +0000
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Subject: [PATCH] drivers: usb: dwc3: add FS/LS bus instance parkmode disable
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bit
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There are three parkmode disable bits, one for each bus instance type.
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Add FS/LS and parse the quirk out of DT. Also update the slightly
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mangled quirk descriptions.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/usb/dwc3/core.c | 5 +++++
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drivers/usb/dwc3/core.h | 12 ++++++++----
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2 files changed, 13 insertions(+), 4 deletions(-)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -1485,6 +1485,9 @@ static int dwc3_core_init(struct dwc3 *d
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if (dwc->parkmode_disable_hs_quirk)
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reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
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+ if (dwc->parkmode_disable_fsls_quirk)
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+ reg |= DWC3_GUCTL1_PARKMODE_DISABLE_FSLS;
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+
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if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
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if (dwc->maximum_speed == USB_SPEED_FULL ||
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dwc->maximum_speed == USB_SPEED_HIGH)
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@@ -1831,6 +1834,8 @@ static void dwc3_get_properties(struct d
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"snps,parkmode-disable-ss-quirk");
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dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
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"snps,parkmode-disable-hs-quirk");
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+ dwc->parkmode_disable_fsls_quirk = device_property_read_bool(dev,
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+ "snps,parkmode-disable-fsls-quirk");
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dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
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"snps,gfladj-refclk-lpm-sel-quirk");
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -284,6 +284,7 @@
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#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
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#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
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#define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16)
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+#define DWC3_GUCTL1_PARKMODE_DISABLE_FSLS BIT(15)
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#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
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/* Global Status Register */
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@@ -1142,10 +1143,12 @@ struct dwc3_scratchpad_array {
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* generation after resume from suspend.
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* @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
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* VBUS with an external supply.
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- * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
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- * instances in park mode.
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- * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
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- * instances in park mode.
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+ * @parkmode_disable_ss_quirk: If set, disable park mode feature for all
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+ * Superspeed instances.
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+ * @parkmode_disable_hs_quirk: If set, disable park mode feature for all
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+ * Highspeed instances.
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+ * @parkmode_disable_fsls_quirk: If set, disable park mode feature for all
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+ * Full/Lowspeed instances.
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* @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter
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* running based on ref_clk
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* @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
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@@ -1385,6 +1388,7 @@ struct dwc3 {
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unsigned ulpi_ext_vbus_drv:1;
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unsigned parkmode_disable_ss_quirk:1;
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unsigned parkmode_disable_hs_quirk:1;
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+ unsigned parkmode_disable_fsls_quirk:1;
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unsigned gfladj_refclk_lpm_sel:1;
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unsigned tx_de_emphasis_quirk:1;
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