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https://github.com/coolsnowwolf/lede.git
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d81c03f05e
These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.12.y With the following command: git format-patch -N v6.12.27..HEAD (HEAD -> 8d3206ee456a5ecdf9ddbfd8e5e231e4f0cd716e) Exceptions: - (def)configs patches - github workflows patches - applied & reverted patches - readme patches - wireless patches Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
85 lines
2.3 KiB
Diff
85 lines
2.3 KiB
Diff
From 9211ccc7e1daf8589e095341f616557a0188aac0 Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Tue, 3 Sep 2019 20:28:00 +0100
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Subject: [PATCH] clk-bcm2835: Disable v3d clock
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This is controlled by firmware, see clk-raspberrypi.c
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Signed-off-by: popcornmix <popcornmix@gmail.com>
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clk-bcm2835: Remove VEC clock support
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/clk/bcm/clk-bcm2835.c | 45 ++++++++++-------------------------
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1 file changed, 12 insertions(+), 33 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1764,16 +1764,12 @@ static const struct bcm2835_clk_desc clk
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.hold_mask = CM_PLLA_HOLDCORE,
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
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- [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
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- SOC_ALL,
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- .name = "plla_per",
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- .source_pll = "plla",
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- .cm_reg = CM_PLLA,
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- .a2w_reg = A2W_PLLA_PER,
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- .load_mask = CM_PLLA_LOADPER,
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- .hold_mask = CM_PLLA_HOLDPER,
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- .fixed_divider = 1,
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- .flags = CLK_SET_RATE_PARENT),
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+
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+ /*
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+ * PLLA_PER is used for gpu clocks. Controlled by firmware, see
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+ * clk-raspberrypi.c.
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+ */
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+
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[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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SOC_ALL,
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.name = "plla_dsi0",
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@@ -2074,14 +2070,12 @@ static const struct bcm2835_clk_desc clk
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.int_bits = 6,
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.frac_bits = 0,
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.tcnt_mux = 3),
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- [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
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- SOC_ALL,
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- .name = "v3d",
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- .ctl_reg = CM_V3DCTL,
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- .div_reg = CM_V3DDIV,
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- .int_bits = 4,
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- .frac_bits = 8,
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- .tcnt_mux = 4),
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+
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+ /*
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+ * CLOCK_V3D is used for v3d clock. Controlled by firmware, see
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+ * clk-raspberrypi.c.
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+ */
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+
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/*
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* VPU clock. This doesn't have an enable bit, since it drives
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* the bus for everything else, and is special so it doesn't need
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@@ -2244,21 +2238,6 @@ static const struct bcm2835_clk_desc clk
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.tcnt_mux = 28,
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.round_up = true),
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- /* TV encoder clock. Only operating frequency is 108Mhz. */
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- [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
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- SOC_ALL,
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- .name = "vec",
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- .ctl_reg = CM_VECCTL,
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- .div_reg = CM_VECDIV,
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- .int_bits = 4,
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- .frac_bits = 0,
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- /*
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- * Allow rate change propagation only on PLLH_AUX which is
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- * assigned index 7 in the parent array.
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- */
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- .set_rate_parent = BIT(7),
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- .tcnt_mux = 29),
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-
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/* dsi clocks */
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[BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
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SOC_ALL,
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