mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 04:13:31 +00:00
94 lines
3.3 KiB
Diff
94 lines
3.3 KiB
Diff
From a9d37e684492ab5db1cce28b655e20c01191873f Mon Sep 17 00:00:00 2001
|
|
From: Sascha Hauer <s.hauer@pengutronix.de>
|
|
Date: Fri, 22 Apr 2022 09:28:21 +0200
|
|
Subject: [PATCH] drm/rockchip: dw_hdmi: rename vpll clock to reference clock
|
|
|
|
"vpll" is a misnomer. A clock input to a device should be named after
|
|
the usage in the device, not after the clock that drives it. On the
|
|
rk3568 the same clock is driven by the HPLL.
|
|
To fix that, this patch renames the vpll clock to ref clock. The clock
|
|
name "vpll" is left for compatibility to old device trees.
|
|
|
|
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
|
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
|
|
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
|
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
|
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-5-s.hauer@pengutronix.de
|
|
---
|
|
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 27 +++++++++++----------
|
|
1 file changed, 14 insertions(+), 13 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
|
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
|
|
@@ -69,7 +69,7 @@ struct rockchip_hdmi {
|
|
struct regmap *regmap;
|
|
struct rockchip_encoder encoder;
|
|
const struct rockchip_hdmi_chip_data *chip_data;
|
|
- struct clk *vpll_clk;
|
|
+ struct clk *ref_clk;
|
|
struct clk *grf_clk;
|
|
struct dw_hdmi *hdmi;
|
|
struct phy *phy;
|
|
@@ -201,14 +201,15 @@ static int rockchip_hdmi_parse_dt(struct
|
|
return PTR_ERR(hdmi->regmap);
|
|
}
|
|
|
|
- hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
|
|
- if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
|
|
- hdmi->vpll_clk = NULL;
|
|
- } else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
|
|
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "ref");
|
|
+ if (!hdmi->ref_clk)
|
|
+ hdmi->ref_clk = devm_clk_get_optional(hdmi->dev, "vpll");
|
|
+
|
|
+ if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
|
|
return -EPROBE_DEFER;
|
|
- } else if (IS_ERR(hdmi->vpll_clk)) {
|
|
- DRM_DEV_ERROR(hdmi->dev, "failed to get grf clock\n");
|
|
- return PTR_ERR(hdmi->vpll_clk);
|
|
+ } else if (IS_ERR(hdmi->ref_clk)) {
|
|
+ DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
|
|
+ return PTR_ERR(hdmi->ref_clk);
|
|
}
|
|
|
|
hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
|
|
@@ -262,7 +263,7 @@ static void dw_hdmi_rockchip_encoder_mod
|
|
{
|
|
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
|
|
|
|
- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
|
|
+ clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
|
|
}
|
|
|
|
static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
|
|
@@ -542,9 +543,9 @@ static int dw_hdmi_rockchip_bind(struct
|
|
return ret;
|
|
}
|
|
|
|
- ret = clk_prepare_enable(hdmi->vpll_clk);
|
|
+ ret = clk_prepare_enable(hdmi->ref_clk);
|
|
if (ret) {
|
|
- DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
|
|
+ DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
@@ -563,7 +564,7 @@ static int dw_hdmi_rockchip_bind(struct
|
|
if (IS_ERR(hdmi->hdmi)) {
|
|
ret = PTR_ERR(hdmi->hdmi);
|
|
drm_encoder_cleanup(encoder);
|
|
- clk_disable_unprepare(hdmi->vpll_clk);
|
|
+ clk_disable_unprepare(hdmi->ref_clk);
|
|
}
|
|
|
|
return ret;
|
|
@@ -575,7 +576,7 @@ static void dw_hdmi_rockchip_unbind(stru
|
|
struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
|
|
|
|
dw_hdmi_unbind(hdmi->hdmi);
|
|
- clk_disable_unprepare(hdmi->vpll_clk);
|
|
+ clk_disable_unprepare(hdmi->ref_clk);
|
|
}
|
|
|
|
static const struct component_ops dw_hdmi_rockchip_ops = {
|