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45 lines
1.4 KiB
Diff
45 lines
1.4 KiB
Diff
From cef0d7940ff741590c638ced909cb9e58b9d8bb0 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 28 Dec 2021 20:59:18 +0100
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Subject: [PATCH] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller
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support
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IPQ8074 has the APSS clock controller utilizing the same register space as
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the APCS, so provide acess to the APSS utilizing a child device like
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IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
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clock driver.
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Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
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updated to 0x5FFC.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/mailbox/qcom-apcs-ipc-mailbox.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
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index 82ccfaf14b24..23407280580f 100644
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--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
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+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
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@@ -34,7 +34,7 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
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};
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static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
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- .offset = 8, .clk_name = NULL
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+ .offset = 8, .clk_name = "qcom,apss-ipq8074-clk"
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};
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static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
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@@ -73,7 +73,7 @@ static const struct regmap_config apcs_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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- .max_register = 0x1008,
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+ .max_register = 0x5FFC,
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.fast_io = true,
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};
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--
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2.35.1
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