mirror of
https://github.com/coolsnowwolf/lede.git
synced 2025-04-16 14:23:38 +00:00
75 lines
2.7 KiB
Diff
75 lines
2.7 KiB
Diff
From 31aeaf547d7e3b64ba5d5442dabc530bdb9e216e Mon Sep 17 00:00:00 2001
|
|
From: Karthikeyan Periyasamy <quic_periyasa@quicinc.com>
|
|
Date: Wed, 10 Nov 2021 21:51:30 +0530
|
|
Subject: [PATCH 071/120] ath11k: fix DMA memory free in CE pipe cleanup
|
|
|
|
In CE pipe cleanup, DMA memory gets freed by the aligned address
|
|
(base_addr_owner_space) which is wrong. It needs to be freed
|
|
by the address (base_addr_owner_space_unaligned) returned by
|
|
dma_alloc. So free the dma memory by the proper address.
|
|
This was found in code review.
|
|
|
|
Tested-on: IPQ8074 hw2.0 AHB WLAN.HK.2.5.0.1-00729-QCAHKSWPL_SILICONZ-3 v2
|
|
|
|
Signed-off-by: Karthikeyan Periyasamy <quic_periyasa@quicinc.com>
|
|
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
|
|
Link: https://lore.kernel.org/r/1636561290-18966-1-git-send-email-quic_periyasa@quicinc.com
|
|
---
|
|
drivers/net/wireless/ath/ath11k/ce.c | 16 ++++++++++------
|
|
1 file changed, 10 insertions(+), 6 deletions(-)
|
|
|
|
--- a/drivers/net/wireless/ath/ath11k/ce.c
|
|
+++ b/drivers/net/wireless/ath/ath11k/ce.c
|
|
@@ -953,6 +953,7 @@ int ath11k_ce_init_pipes(struct ath11k_b
|
|
void ath11k_ce_free_pipes(struct ath11k_base *ab)
|
|
{
|
|
struct ath11k_ce_pipe *pipe;
|
|
+ struct ath11k_ce_ring *ce_ring;
|
|
int desc_sz;
|
|
int i;
|
|
|
|
@@ -964,22 +965,24 @@ void ath11k_ce_free_pipes(struct ath11k_
|
|
|
|
if (pipe->src_ring) {
|
|
desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_SRC);
|
|
+ ce_ring = pipe->src_ring;
|
|
dma_free_coherent(ab->dev,
|
|
pipe->src_ring->nentries * desc_sz +
|
|
CE_DESC_RING_ALIGN,
|
|
- pipe->src_ring->base_addr_owner_space,
|
|
- pipe->src_ring->base_addr_ce_space);
|
|
+ ce_ring->base_addr_owner_space_unaligned,
|
|
+ ce_ring->base_addr_ce_space_unaligned);
|
|
kfree(pipe->src_ring);
|
|
pipe->src_ring = NULL;
|
|
}
|
|
|
|
if (pipe->dest_ring) {
|
|
desc_sz = ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST);
|
|
+ ce_ring = pipe->dest_ring;
|
|
dma_free_coherent(ab->dev,
|
|
pipe->dest_ring->nentries * desc_sz +
|
|
CE_DESC_RING_ALIGN,
|
|
- pipe->dest_ring->base_addr_owner_space,
|
|
- pipe->dest_ring->base_addr_ce_space);
|
|
+ ce_ring->base_addr_owner_space_unaligned,
|
|
+ ce_ring->base_addr_ce_space_unaligned);
|
|
kfree(pipe->dest_ring);
|
|
pipe->dest_ring = NULL;
|
|
}
|
|
@@ -987,11 +990,12 @@ void ath11k_ce_free_pipes(struct ath11k_
|
|
if (pipe->status_ring) {
|
|
desc_sz =
|
|
ath11k_hal_ce_get_desc_size(HAL_CE_DESC_DST_STATUS);
|
|
+ ce_ring = pipe->status_ring;
|
|
dma_free_coherent(ab->dev,
|
|
pipe->status_ring->nentries * desc_sz +
|
|
CE_DESC_RING_ALIGN,
|
|
- pipe->status_ring->base_addr_owner_space,
|
|
- pipe->status_ring->base_addr_ce_space);
|
|
+ ce_ring->base_addr_owner_space_unaligned,
|
|
+ ce_ring->base_addr_ce_space_unaligned);
|
|
kfree(pipe->status_ring);
|
|
pipe->status_ring = NULL;
|
|
}
|