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347559c17a
lede/target/linux/rockchip/patches-5.19/0800-rockchip-snps-pcie3-update-fw-when-init.patch
aakkll 347559c17a
kernel: refresh 5.19 patch (#9943) 
Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>

Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>
2022-08-14 23:35:01 +08:00

8275 lines
75 KiB
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From c056c33a88c05d64bfac3687e6fbab978c7d1f57 Mon Sep 17 00:00:00 2001
From: Kever Yang <kever.yang@rock-chips.com>
Date: Fri, 13 May 2022 09:54:12 +0800
Subject: [PATCH] phy: rockchip-snps-pcie3: update fw when init
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: jensen <jensenhuang@friendlyarm.com>
---
drivers/phy/rockchip/p3phy.fw | 8192 +++++++++++++++++
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +-
2 files changed, 8220 insertions(+), 9 deletions(-)
create mode 100644 drivers/phy/rockchip/p3phy.fw
--- /dev/null
+++ b/drivers/phy/rockchip/p3phy.fw
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -20,6 +20,7 @@
/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1 0x4
+#define GRF_PCIE30PHY_CON4 0x10
#define GRF_PCIE30PHY_CON6 0x18
#define GRF_PCIE30PHY_CON9 0x24
#define GRF_PCIE30PHY_STATUS0 0x80
@@ -61,6 +62,10 @@ struct rockchip_p3phy_ops {
int (*phy_init)(struct rockchip_p3phy_priv *priv);
};
+static u16 phy_fw[] = {
+ #include "p3phy.fw"
+};
+
static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
@@ -86,6 +91,7 @@ static int rockchip_p3phy_rk3568_init(st
struct phy *phy = priv->phy;
bool bifurcation = false;
int ret;
+ int i;
u32 reg;
/* Deassert PCIe PMA output clamp mode */
@@ -110,16 +116,35 @@ static int rockchip_p3phy_rk3568_init(st
(0xf << 16) & ~RK3568_BIFURCATION_LANE_0_1);
}
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x0 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x0 << 13) | (0x1 << (13 + 16))); //sdram_bypass
+
reset_control_deassert(priv->p30phy);
ret = regmap_read_poll_timeout(priv->phy_grf,
GRF_PCIE30PHY_STATUS0,
reg, SRAM_INIT_DONE(reg),
0, 500);
- if (ret)
+ if (ret) {
dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
__func__, reg);
return ret;
+ }
+
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+ (0x3 << 8) | (0x3 << (8 + 16))); //map to access sram
+ for (i = 0; i < 8192; i++)
+ writel(phy_fw[i], priv->mmio + (i<<2));
+
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
+ (0x0 << 8) | (0x3 << (8 + 16)));
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON4,
+ (0x1 << 14) | (0x1 << (14 + 16))); //sdram_ld_done
+
+ dev_info(&priv->phy->dev, "p3phy (fw-d54d0eb) initialized\n");
+ return 0;
}
static const struct rockchip_p3phy_ops rk3568_ops = {
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