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2b9548669a
* Rockchip:Fix dtsi of doornet2 phy: Modify phy timing;The manufacturer's board requires two timing modes: 125m and 25m ---stmmac_mdio.c stmmac_main.c Among them, stmmac_main.c is added with 1.5 reset, and the compilation of other devices is not affected emmc: In emmc hs400 mode, the performance test effect is the same as hs200, so it is safer to reduce hs200 * Rockchip:Add doornet2 to overclock to 2.2GHz/1.8GHz * Create 105-rockchip-rk3399-Add-support-for-EmbedFire-DoorNet2.patch Modify the startup method: SD starts first, which is convenient for saving bricks. If there is no system in SD, it will automatically jump to the next emmc boot * Update with kernel 5.4 * Update 992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch
195 lines
4.2 KiB
Diff
195 lines
4.2 KiB
Diff
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Sat, 19 Dec 2020 12:42:27 +0000
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Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices
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It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
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and for better performance.
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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Co-authored-by: gzelvis <gzelvis@gmail.com>
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---
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.../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++
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.../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +-
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2 files changed, 157 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
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@@ -0,0 +1,152 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
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+ *
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+ * Copyright (c) 2020 Tianling Shen <cnsztl@gmail.com>
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+ * Copyright (c) 2020 gzelvis <gzelvis@gmail.com>
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+ */
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+
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+/ {
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+ cluster0_opp: opp-table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <800000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <800000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <850000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <925000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <1000000>;
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+ };
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+ opp05 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1125000>;
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+ };
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+ opp06 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <1225000>;
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+ };
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+ opp07 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <1275000>;
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+ };
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+ };
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+
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+ cluster1_opp: opp-table1 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <408000000>;
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+ opp-microvolt = <800000>;
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+ clock-latency-ns = <40000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <800000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <816000000>;
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+ opp-microvolt = <825000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <875000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <1200000000>;
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+ opp-microvolt = <950000>;
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+ };
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+ opp05 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <1025000>;
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+ };
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+ opp06 {
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+ opp-hz = /bits/ 64 <1608000000>;
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+ opp-microvolt = <1100000>;
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+ };
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+ opp07 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <1200000>;
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+ };
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+ opp08 {
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+ opp-hz = /bits/ 64 <2016000000>;
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+ opp-microvolt = <1250000>;
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+ };
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+ opp09 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <1325000>;
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+ };
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+ };
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+
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+ gpu_opp_table: opp-table2 {
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+ compatible = "operating-points-v2";
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+
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+ opp00 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ opp-microvolt = <800000>;
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+ };
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+ opp01 {
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+ opp-hz = /bits/ 64 <297000000>;
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+ opp-microvolt = <800000>;
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+ };
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+ opp02 {
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+ opp-hz = /bits/ 64 <400000000>;
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+ opp-microvolt = <825000>;
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+ };
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+ opp03 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ opp-microvolt = <875000>;
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+ };
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+ opp04 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <925000>;
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+ };
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+ opp05 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1100000>;
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+ };
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+ };
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+};
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+
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+&cpu_l0 {
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+ operating-points-v2 = <&cluster0_opp>;
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+};
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+
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+&cpu_l1 {
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+ operating-points-v2 = <&cluster0_opp>;
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+};
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+
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+&cpu_l2 {
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+ operating-points-v2 = <&cluster0_opp>;
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+};
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+
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+&cpu_l3 {
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+ operating-points-v2 = <&cluster0_opp>;
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+};
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+
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+&cpu_b0 {
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+ operating-points-v2 = <&cluster1_opp>;
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+};
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+
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+&cpu_b1 {
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+ operating-points-v2 = <&cluster1_opp>;
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+};
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+
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+&gpu {
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+ operating-points-v2 = <&gpu_opp_table>;
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
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@@ -14,7 +14,7 @@
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/dts-v1/;
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#include <dt-bindings/input/linux-event-codes.h>
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#include "rk3399.dtsi"
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-#include "rk3399-opp.dtsi"
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+#include "rk3399-nanopi4-opp.dtsi"
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/ {
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chosen {
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--- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi
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@@ -3,7 +3,7 @@
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/dts-v1/;
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#include <dt-bindings/input/linux-event-codes.h>
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#include "rk3399.dtsi"
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-#include "rk3399-opp.dtsi"
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+#include "rk3399-nanopi4-opp.dtsi"
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/ {
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chosen {
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