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2b67b80839
Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com> Signed-off-by: aakkll <94471752+aakkll@users.noreply.github.com>
42 lines
1.1 KiB
Diff
42 lines
1.1 KiB
Diff
From 591f44f27342906ccd58eb7e63ec3ef5810bd7eb Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 11 May 2022 11:01:17 -0400
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Subject: [PATCH 03/51] arm64: dts: rockchip: enable sfc controller on Quartz64
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Model A
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Add the sfc controller binding for the Quartz64 Model A. This is not
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populated by default, so leave it disabled.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
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@@ -616,6 +616,22 @@
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status = "okay";
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};
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+&sfc {
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+ pinctrl-0 = <&fspi_pins>;
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+ pinctrl-names = "default";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <24000000>;
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+ spi-rx-bus-width = <4>;
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+ spi-tx-bus-width = <1>;
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+ };
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+};
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+
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/* spdif is exposed on con40 pin 18 */
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&spdif {
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status = "okay";
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