mirror of
https://github.com/coolsnowwolf/lede.git
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520 lines
12 KiB
Diff
520 lines
12 KiB
Diff
From 0f868f286529001ee37334815f4962b8a2f283dd Mon Sep 17 00:00:00 2001
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From: Anusha Rao <quic_anusha@quicinc.com>
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Date: Wed, 27 Sep 2023 12:13:18 +0530
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Subject: [PATCH 34/41] arm64: dts: qcom: ipq9574: Add common RDP dtsi file
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Add a dtsi file to include interfaces that are common
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across RDPs.
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Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Link: https://lore.kernel.org/r/20230927-common-rdp-v3-1-3d07b3ff6d42@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 102 ++++++++++++++++++
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arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 63 +----------
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arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 38 +------
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arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts | 65 +----------
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arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 65 +----------
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arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 66 +-----------
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6 files changed, 107 insertions(+), 292 deletions(-)
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create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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new file mode 100644
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index 000000000000..c935ac53efe6
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--- /dev/null
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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@@ -0,0 +1,102 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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+/*
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+ * IPQ9574 RDP board common device tree source
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+ *
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+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/dts-v1/;
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+
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+#include "ipq9574.dtsi"
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+
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+/ {
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+ aliases {
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+ serial0 = &blsp1_uart2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ regulator_fixed_3p3: s3300 {
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+ compatible = "regulator-fixed";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-name = "fixed_3p3";
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+ };
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+
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+ regulator_fixed_0p925: s0925 {
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+ compatible = "regulator-fixed";
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+ regulator-min-microvolt = <925000>;
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+ regulator-max-microvolt = <925000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ regulator-name = "fixed_0p925";
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+ };
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+};
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+
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+&blsp1_spi0 {
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+ pinctrl-0 = <&spi_0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "micron,n25q128a11", "jedec,spi-nor";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <50000000>;
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+ };
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+};
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+
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+&blsp1_uart2 {
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+ pinctrl-0 = <&uart2_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&rpm_requests {
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+ regulators {
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+ compatible = "qcom,rpm-mp5496-regulators";
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+
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+ ipq9574_s1: s1 {
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+ /*
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+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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+ * During regulator registration, kernel not knowing the initial voltage,
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+ * considers it as zero and brings up the regulators with minimum supported voltage.
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+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
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+ * the regulators are brought up with 725mV which is sufficient for all the
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+ * corner parts to operate at 800MHz
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+ */
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+ regulator-min-microvolt = <725000>;
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+ regulator-max-microvolt = <1075000>;
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+ };
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+
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+ mp5496_l2: l2 {
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-always-on;
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+ regulator-boot-on;
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+ };
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+ };
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+};
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+
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+&sleep_clk {
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+ clock-frequency = <32000>;
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+};
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+
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+&tlmm {
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+ spi_0_pins: spi-0-state {
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+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
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+ function = "blsp0_spi";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+};
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+
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+&xo_board_clk {
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+ clock-frequency = <24000000>;
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+};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
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index 2b093e02637b..f4f9199d4ab1 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts
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@@ -8,58 +8,12 @@
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/dts-v1/;
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-#include "ipq9574.dtsi"
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+#include "ipq9574-rdp-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2";
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compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574";
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-};
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-
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-&blsp1_spi0 {
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- pinctrl-0 = <&spi_0_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-
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- flash@0 {
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- compatible = "micron,n25q128a11", "jedec,spi-nor";
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- reg = <0>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- spi-max-frequency = <50000000>;
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- };
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-};
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-
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-&blsp1_uart2 {
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- pinctrl-0 = <&uart2_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-};
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-
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-&rpm_requests {
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- regulators {
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- compatible = "qcom,rpm-mp5496-regulators";
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-
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- ipq9574_s1: s1 {
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- /*
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- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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- * During regulator registration, kernel not knowing the initial voltage,
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- * considers it as zero and brings up the regulators with minimum supported voltage.
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- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
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- * the regulators are brought up with 725mV which is sufficient for all the
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- * corner parts to operate at 800MHz
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- */
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- regulator-min-microvolt = <725000>;
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- regulator-max-microvolt = <1075000>;
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- };
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- };
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};
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&sdhc_1 {
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@@ -74,10 +28,6 @@ &sdhc_1 {
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status = "okay";
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};
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-&sleep_clk {
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- clock-frequency = <32000>;
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-};
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-
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&tlmm {
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sdc_default_state: sdc-default-state {
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clk-pins {
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@@ -110,15 +60,4 @@ rclk-pins {
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bias-pull-down;
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};
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};
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-
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- spi_0_pins: spi-0-state {
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- pins = "gpio11", "gpio12", "gpio13", "gpio14";
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- function = "blsp0_spi";
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- drive-strength = <8>;
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- bias-disable;
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- };
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-};
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-
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-&xo_board_clk {
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- clock-frequency = <24000000>;
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};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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index 2b3ed8d351f7..16217471893d 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -8,44 +8,12 @@
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/dts-v1/;
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-#include "ipq9574.dtsi"
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+#include "ipq9574-rdp-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
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compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-};
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-
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-&blsp1_uart2 {
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- pinctrl-0 = <&uart2_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-};
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-
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-&rpm_requests {
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- regulators {
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- compatible = "qcom,rpm-mp5496-regulators";
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-
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- ipq9574_s1: s1 {
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- /*
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- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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- * During regulator registration, kernel not knowing the initial voltage,
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- * considers it as zero and brings up the regulators with minimum supported voltage.
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- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
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- * the regulators are brought up with 725mV which is sufficient for all the
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- * corner parts to operate at 800MHz
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- */
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- regulator-min-microvolt = <725000>;
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- regulator-max-microvolt = <1075000>;
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- };
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- };
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};
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&sdhc_1 {
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@@ -97,7 +65,3 @@ rclk-pins {
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};
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};
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};
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-
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-&xo_board_clk {
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- clock-frequency = <24000000>;
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-};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
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index c8fa54e1a62c..d36d1078763e 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts
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@@ -8,73 +8,10 @@
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/dts-v1/;
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-#include "ipq9574.dtsi"
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+#include "ipq9574-rdp-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6";
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compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574";
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-};
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-
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-&blsp1_spi0 {
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- pinctrl-0 = <&spi_0_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-
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- flash@0 {
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- compatible = "micron,n25q128a11", "jedec,spi-nor";
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- reg = <0>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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- spi-max-frequency = <50000000>;
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- };
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-};
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-
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-&blsp1_uart2 {
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- pinctrl-0 = <&uart2_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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-};
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-
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-&rpm_requests {
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- regulators {
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- compatible = "qcom,rpm-mp5496-regulators";
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-
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- ipq9574_s1: s1 {
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- /*
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- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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- * During regulator registration, kernel not knowing the initial voltage,
|
|
- * considers it as zero and brings up the regulators with minimum supported voltage.
|
|
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
|
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- * the regulators are brought up with 725mV which is sufficient for all the
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- * corner parts to operate at 800MHz
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- */
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- regulator-min-microvolt = <725000>;
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- regulator-max-microvolt = <1075000>;
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- };
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- };
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-};
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-
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-&sleep_clk {
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- clock-frequency = <32000>;
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-};
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-
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-&tlmm {
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- spi_0_pins: spi-0-state {
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- pins = "gpio11", "gpio12", "gpio13", "gpio14";
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- function = "blsp0_spi";
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- drive-strength = <8>;
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- bias-disable;
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- };
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-};
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-
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-&xo_board_clk {
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- clock-frequency = <24000000>;
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};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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index f01de6628c3b..c30c9fbedf26 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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@@ -8,73 +8,10 @@
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/dts-v1/;
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-#include "ipq9574.dtsi"
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+#include "ipq9574-rdp-common.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
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compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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-};
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-
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-&blsp1_spi0 {
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- pinctrl-0 = <&spi_0_pins>;
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- pinctrl-names = "default";
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- status = "okay";
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|
-
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- flash@0 {
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- compatible = "micron,n25q128a11", "jedec,spi-nor";
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- reg = <0>;
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- #address-cells = <1>;
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|
- #size-cells = <1>;
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|
- spi-max-frequency = <50000000>;
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|
- };
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|
-};
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-
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-&blsp1_uart2 {
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- pinctrl-0 = <&uart2_pins>;
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- pinctrl-names = "default";
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- status = "okay";
|
|
-};
|
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-
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-&rpm_requests {
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- regulators {
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- compatible = "qcom,rpm-mp5496-regulators";
|
|
-
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- ipq9574_s1: s1 {
|
|
- /*
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|
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
|
|
- * During regulator registration, kernel not knowing the initial voltage,
|
|
- * considers it as zero and brings up the regulators with minimum supported voltage.
|
|
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
|
|
- * the regulators are brought up with 725mV which is sufficient for all the
|
|
- * corner parts to operate at 800MHz
|
|
- */
|
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- regulator-min-microvolt = <725000>;
|
|
- regulator-max-microvolt = <1075000>;
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|
- };
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- };
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-};
|
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-
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-&sleep_clk {
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- clock-frequency = <32000>;
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|
-};
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-
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-&tlmm {
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- spi_0_pins: spi-0-state {
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- pins = "gpio11", "gpio12", "gpio13", "gpio14";
|
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- function = "blsp0_spi";
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|
- drive-strength = <8>;
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- bias-disable;
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- };
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-};
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|
-
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-&xo_board_clk {
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|
- clock-frequency = <24000000>;
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|
};
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|
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
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|
index 6efae3426cb8..0dc382f5d5ec 100644
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|
--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
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|
+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts
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|
@@ -8,73 +8,9 @@
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|
|
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/dts-v1/;
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|
|
|
-#include "ipq9574.dtsi"
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+#include "ipq9574-rdp-common.dtsi"
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|
|
|
/ {
|
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model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9";
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compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574";
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-
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- aliases {
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- serial0 = &blsp1_uart2;
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- };
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-
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- chosen {
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- stdout-path = "serial0:115200n8";
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- };
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|
-};
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-
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-&blsp1_spi0 {
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- pinctrl-0 = <&spi_0_pins>;
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|
- pinctrl-names = "default";
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|
- status = "okay";
|
|
-
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|
- flash@0 {
|
|
- compatible = "micron,n25q128a11", "jedec,spi-nor";
|
|
- reg = <0>;
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- spi-max-frequency = <50000000>;
|
|
- };
|
|
-};
|
|
-
|
|
-&blsp1_uart2 {
|
|
- pinctrl-0 = <&uart2_pins>;
|
|
- pinctrl-names = "default";
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&rpm_requests {
|
|
- regulators {
|
|
- compatible = "qcom,rpm-mp5496-regulators";
|
|
-
|
|
- ipq9574_s1: s1 {
|
|
- /*
|
|
- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
|
|
- * During regulator registration, kernel not knowing the initial voltage,
|
|
- * considers it as zero and brings up the regulators with minimum supported voltage.
|
|
- * Update the regulator-min-microvolt with SVS voltage of 725mV so that
|
|
- * the regulators are brought up with 725mV which is sufficient for all the
|
|
- * corner parts to operate at 800MHz
|
|
- */
|
|
- regulator-min-microvolt = <725000>;
|
|
- regulator-max-microvolt = <1075000>;
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&sleep_clk {
|
|
- clock-frequency = <32000>;
|
|
-};
|
|
-
|
|
-&tlmm {
|
|
- spi_0_pins: spi-0-state {
|
|
- pins = "gpio11", "gpio12", "gpio13", "gpio14";
|
|
- function = "blsp0_spi";
|
|
- drive-strength = <8>;
|
|
- bias-disable;
|
|
- };
|
|
-};
|
|
-
|
|
-&xo_board_clk {
|
|
- clock-frequency = <24000000>;
|
|
};
|
|
--
|
|
2.34.1
|
|
|