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121 lines
3.4 KiB
Diff
121 lines
3.4 KiB
Diff
From cc88e897a8fe19d2a611a51321577c11a7997e68 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Fri, 26 May 2023 21:01:52 +0530
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Subject: [PATCH 25/41] arm64: dts: qcom: ipq9574: add support for RDP453
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variant
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Add the initial device tree support for the Reference Design Platform (RDP)
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453 based on IPQ9574 family of SoCs. This patch adds support for Console
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UART, SPI NOR and SMPA1 regulator node.
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230526153152.777-3-quic_devipriy@quicinc.com
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---
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arch/arm64/boot/dts/qcom/Makefile | 1 +
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arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 80 +++++++++++++++++++++
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2 files changed, 81 insertions(+)
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create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
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index f237a3683ca4..082a5c975288 100644
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--- a/arch/arm64/boot/dts/qcom/Makefile
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+++ b/arch/arm64/boot/dts/qcom/Makefile
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@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb
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dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb
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+dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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new file mode 100644
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index 000000000000..f01de6628c3b
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--- /dev/null
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts
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@@ -0,0 +1,80 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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+/*
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+ * IPQ9574 RDP453 board device tree source
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+ *
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+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+/dts-v1/;
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+
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+#include "ipq9574.dtsi"
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+
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+/ {
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+ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8";
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+ compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574";
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+
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+ aliases {
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+ serial0 = &blsp1_uart2;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+};
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+
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+&blsp1_spi0 {
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+ pinctrl-0 = <&spi_0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "micron,n25q128a11", "jedec,spi-nor";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <50000000>;
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+ };
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+};
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+
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+&blsp1_uart2 {
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+ pinctrl-0 = <&uart2_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&rpm_requests {
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+ regulators {
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+ compatible = "qcom,rpm-mp5496-regulators";
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+
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+ ipq9574_s1: s1 {
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+ /*
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+ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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+ * During regulator registration, kernel not knowing the initial voltage,
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+ * considers it as zero and brings up the regulators with minimum supported voltage.
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+ * Update the regulator-min-microvolt with SVS voltage of 725mV so that
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+ * the regulators are brought up with 725mV which is sufficient for all the
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+ * corner parts to operate at 800MHz
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+ */
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+ regulator-min-microvolt = <725000>;
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+ regulator-max-microvolt = <1075000>;
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+ };
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+ };
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+};
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+
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+&sleep_clk {
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+ clock-frequency = <32000>;
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+};
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+
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+&tlmm {
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+ spi_0_pins: spi-0-state {
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+ pins = "gpio11", "gpio12", "gpio13", "gpio14";
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+ function = "blsp0_spi";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+};
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+
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+&xo_board_clk {
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+ clock-frequency = <24000000>;
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+};
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--
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2.34.1
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