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128 lines
3.5 KiB
Diff
128 lines
3.5 KiB
Diff
From 13ad51cfa78defdafd717ed89785c7bab8330a7b Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Wed, 17 May 2023 22:55:27 +0530
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Subject: [PATCH 19/41] arm64: dts: qcom: ipq9574: Add cpufreq support
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Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
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Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230517172527.1968-4-quic_devipriy@quicinc.com
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++-
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1 file changed, 59 insertions(+), 1 deletion(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index a8ce148e52e4..2d0a10f6c302 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -6,8 +6,9 @@
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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-#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/clock/qcom,apss-ipq.h>
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#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
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/ {
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@@ -37,6 +38,10 @@ CPU0: cpu@0 {
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reg = <0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <&ipq9574_s1>;
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};
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CPU1: cpu@1 {
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@@ -45,6 +50,10 @@ CPU1: cpu@1 {
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reg = <0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <&ipq9574_s1>;
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};
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CPU2: cpu@2 {
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@@ -53,6 +62,10 @@ CPU2: cpu@2 {
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reg = <0x2>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <&ipq9574_s1>;
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};
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CPU3: cpu@3 {
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@@ -61,6 +74,10 @@ CPU3: cpu@3 {
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reg = <0x3>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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+ cpu-supply = <&ipq9574_s1>;
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};
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L2_0: l2-cache {
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@@ -75,6 +92,47 @@ memory@40000000 {
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reg = <0x0 0x40000000 0x0 0x0>;
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};
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+ cpu_opp_table: opp-table-cpu {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-936000000 {
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+ opp-hz = /bits/ 64 <936000000>;
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+ opp-microvolt = <725000>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1104000000 {
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+ opp-hz = /bits/ 64 <1104000000>;
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+ opp-microvolt = <787500>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1416000000 {
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+ opp-hz = /bits/ 64 <1416000000>;
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+ opp-microvolt = <862500>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1488000000 {
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+ opp-hz = /bits/ 64 <1488000000>;
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+ opp-microvolt = <925000>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1800000000 {
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+ opp-hz = /bits/ 64 <1800000000>;
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+ opp-microvolt = <987500>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-2208000000 {
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+ opp-hz = /bits/ 64 <2208000000>;
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+ opp-microvolt = <1062500>;
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+ clock-latency-ns = <200000>;
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+ };
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+ };
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+
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pmu {
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compatible = "arm,cortex-a73-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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--
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2.34.1
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