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43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
From d7a20702b072333cc36cc78eb715295d65159196 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Tue, 25 Apr 2023 14:10:05 +0530
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Subject: [PATCH 15/41] arm64: dts: qcom: ipq9574: Update the size of GICC &
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GICV regions
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Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR
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registers lie in the second 4kB region. Also, add target CPU encoding.
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Fixes: 97cb36ff52a1 ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support")
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20230425084010.15581-2-quic_devipriy@quicinc.com
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index 0b8cd6ca0abe..77fd9b02df69 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -166,14 +166,14 @@ blsp1_uart2: serial@78b1000 {
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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reg = <0x0b000000 0x1000>, /* GICD */
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- <0x0b002000 0x1000>, /* GICC */
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+ <0x0b002000 0x2000>, /* GICC */
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<0x0b001000 0x1000>, /* GICH */
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- <0x0b004000 0x1000>; /* GICV */
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+ <0x0b004000 0x2000>; /* GICV */
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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#interrupt-cells = <3>;
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- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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ranges = <0 0x0b00c000 0x3000>;
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v2m0: v2m@0 {
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--
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2.34.1
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